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2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)最新文献

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Transformer-Coupled D-Band PA with 11.8 dBm $mathrm{P}_{mathrm{sat}}$ and 6.3 % PAE in $0.13 mu mathrm{m}$ SiGe BiCMOS 变压器耦合d波段PA, 11.8 dBm $ mathm {P}_{ mathm {sat}}$和6.3% PAE， $0.13 mu mathm {m}$ SiGe BiCMOS
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2020-01-01 DOI: 10.1109/SIRF46766.2020.9040185
J. Romstadt, V. Lammert, N. Pohl, V. Issakov
{"title":"Transformer-Coupled D-Band PA with 11.8 dBm $mathrm{P}_{mathrm{sat}}$ and 6.3 % PAE in $0.13 mu mathrm{m}$ SiGe BiCMOS","authors":"J. Romstadt, V. Lammert, N. Pohl, V. Issakov","doi":"10.1109/SIRF46766.2020.9040185","DOIUrl":"https://doi.org/10.1109/SIRF46766.2020.9040185","url":null,"abstract":"In this paper we present a fully differential power amplifier (PA) in a $0.13 mu mathrm{m}$ SiGe BiCMOS technology operating in D-Band. The PA has a maximum PAE of 6.3 %, a saturated output power of 11.8 dBm at a frequency of 114 GHz and is designed to an optimum load impedance different from $50 Omega$ offered by a chip to PCB transition. In the previously designed SiGe BiCMOS PAs for D-Band applications, interstage matching networks consist of transmission lines, whereas in this work a transformer is used because a transformer offers the advantage of being an efficient and compact higher-order filter. Therefore, the amplifier only occupies an active chip area of 0.19 mm2 including baluns. In CMOS transformer-based coupling between the stages is quite common, whereas in SiGe this has not been demonstrated so far. Accordingly, to the authors best knowledge, this is the first D-Band SiGe PA using transformer-coupling.","PeriodicalId":221526,"journal":{"name":"2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"1983 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125455114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Power 14% FTR Push-Push D-Band VCO in 130 nm SiGe BiCMOS Technology with −178 dBc/Hz FOMT 一种低功耗14% FTR推推式d波段压控振荡器，采用130nm SiGe BiCMOS技术，fof为- 178 dBc/Hz
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2020-01-01 DOI: 10.1109/SIRF46766.2020.9040174
Sascha Breun, M. Voelkel, Albert-Marcel Schrotz, M. Dietz, V. Issakov, R. Weigel
{"title":"A Low-Power 14% FTR Push-Push D-Band VCO in 130 nm SiGe BiCMOS Technology with −178 dBc/Hz FOMT","authors":"Sascha Breun, M. Voelkel, Albert-Marcel Schrotz, M. Dietz, V. Issakov, R. Weigel","doi":"10.1109/SIRF46766.2020.9040174","DOIUrl":"https://doi.org/10.1109/SIRF46766.2020.9040174","url":null,"abstract":"This paper presents a low-power wideband push-push voltage controlled oscillator (VCO), achieving a frequency tuning-range (FTR) of 19 GHz (14%) at a center frequency of 136 GHz. The VCO yields a minimum phase noise of −86.5 dBc/Hz at 1 MHz offset at a power consumption of around 27 mW from a 1.8 V supply, which yields a $mathrm{FOM}_{mathrm{T}}$ of −178 dBc/Hz. The chip is fabricated using a 130 nm SiGe BiCMOS technology with $f_{mathrm{t}}/f_{max}$ of 250 GHz/370 GHz, respectively, and is integrated with a by-32 divider chain attached to the fundamental output of the VCO, offering a 2.1 GHz output for an external phase-locked loop (PLL).","PeriodicalId":221526,"journal":{"name":"2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132724687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
28 Gbps Bang-Bang CDR for 100G PSM4 with Independently Tunable Proportional and Integral Parameters of the Loop Filter in $0.25 mu mathrm{m}$ Photonic BiCMOS Technology 采用$0.25 mu mathm {m}$光子BiCMOS技术的环路滤波器比例和积分参数可独立调谐，用于100G PSM4的28 Gbps Bang-Bang CDR
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2020-01-01 DOI: 10.1109/SIRF46766.2020.9040190
Mohammed Iftekhar, Sergiy Gudyriev, J. Scheytt
{"title":"28 Gbps Bang-Bang CDR for 100G PSM4 with Independently Tunable Proportional and Integral Parameters of the Loop Filter in $0.25 mu mathrm{m}$ Photonic BiCMOS Technology","authors":"Mohammed Iftekhar, Sergiy Gudyriev, J. Scheytt","doi":"10.1109/SIRF46766.2020.9040190","DOIUrl":"https://doi.org/10.1109/SIRF46766.2020.9040190","url":null,"abstract":"A 28 Gbps NRZ bang-bang clock and data recovery (CDR) chip for 100G PSM4 is presented. It exhibits an adaptable loop filter transfer function with independently tunable proportional and integral parameters. This allows to optimize the jitter transfer, jitter tolerance, and locking range of the CDR according to system requirements. The CDR represents a key component for a single-chip 8-channel electronic-photonic PSM4 transceiver. A CDR chip was manufactured in a $0.25 mu mathrm{m}$ monolithic photonic BiCMOS technology. The core chip area is 0.51 mm2 and it dissipates 330 mW from 2.5 V and 3.3 V power supplies.","PeriodicalId":221526,"journal":{"name":"2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133770850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Full-wave RF Modeling of a Fan-Out Wafer-Level Packaging Technology Based on Al-Al Wafer Bonding 基于Al-Al晶圆键合的扇出晶圆级封装技术的全波射频建模
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2020-01-01 DOI: 10.1109/SIRF46766.2020.9040180
M. Stocchi, M. Wietstruck, S. Schulze, C. Zhibo, S. Tolunay, M. Kaynak
{"title":"Full-wave RF Modeling of a Fan-Out Wafer-Level Packaging Technology Based on Al-Al Wafer Bonding","authors":"M. Stocchi, M. Wietstruck, S. Schulze, C. Zhibo, S. Tolunay, M. Kaynak","doi":"10.1109/SIRF46766.2020.9040180","DOIUrl":"https://doi.org/10.1109/SIRF46766.2020.9040180","url":null,"abstract":"The transmission loss of a test structure, composed of a series of 18 CPW-based interconnections in between a High-Resistive Silicon (HRSi) interposer and a SiGe BiCMOS, produced by using the Al-Al bonding technology for FOWLP is discussed this paper. Its effectiveness as an alternative for mm-wave packaging platforms is proven by an overall $mathrm{S}_{21}$ below 8 dB (< 0.2 dB/transition). Together with the experimental outcomes, the rigorous full-wave modeling of the configuration under investigation is also presented. Particular emphasis is placed on the chosen approach for addressing the criticalities that arise when it comes to simulate structures presenting different scales in their geometry. The validity of the model has been tested against the measured S-parameters, and a good accordance between the latter and the simulated results has been found, which makes the developed numerical platform a reliable tool for further optimization of the next generation of Al-Al FOWLP technology-based devices.","PeriodicalId":221526,"journal":{"name":"2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114535340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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