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2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)最新文献

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A 79 GHz 13.5 dBm $mathbf{P}_{mathrm{sat}}$ at 150°C Transmitter with Compact Local Phase Shifter in 40 nm CMOS for Automotive Radar 用于汽车雷达的79 GHz 13.5 dBm $mathbf{P}_{ mathbf{sat}}$ 150°C的40nm CMOS紧凑本地移相器发射机
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2020-01-01 DOI: 10.1109/SIRF46766.2020.9040196
S. Kishimoto, I. Ando, M. Kohtani, N. Hasegawa, T. Arai, S. Yamaura
{"title":"A 79 GHz 13.5 dBm $mathbf{P}_{mathrm{sat}}$ at 150°C Transmitter with Compact Local Phase Shifter in 40 nm CMOS for Automotive Radar","authors":"S. Kishimoto, I. Ando, M. Kohtani, N. Hasegawa, T. Arai, S. Yamaura","doi":"10.1109/SIRF46766.2020.9040196","DOIUrl":"https://doi.org/10.1109/SIRF46766.2020.9040196","url":null,"abstract":"This paper presents a 79 GHz transmitter with a saturation output power of more than 13.5 dBm at 150°C for automotive radar applications. It includes a phase shifter, a doubler, a variable gain amplifier, a power amplifier and a power detector. A compact fully differential reflection-type phase shifter has been developed at a local frequency band of 40 GHz. A power amplifier is operated with a low supply voltage of 0.9 V to avoid a reliability degradation due to hot carrier injection. The transmitter demonstrates the output power and a maximum phase shift of more than 360° at 150°C from 75 GHz to 82 GHz. A total current consumption is 770 mA at 150°C. The transmitter is implemented using 40 nm CMOS technology. The size is $500 mu mathrm{m}times 800mu mathrm{m}$.","PeriodicalId":221526,"journal":{"name":"2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116938393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low-Loss Ka-band SPDT Switch Design Methodology for 5G Applications in 65 nm CMOS SOI Technology 基于65nm CMOS SOI技术的5G低损耗ka波段SPDT开关设计方法
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2020-01-01 DOI: 10.1109/SIRF46766.2020.9040177
Thibaut Despoisse, N. Deltimple, A. Ghiotto, M. D. Matos, P. Busson
{"title":"Low-Loss Ka-band SPDT Switch Design Methodology for 5G Applications in 65 nm CMOS SOI Technology","authors":"Thibaut Despoisse, N. Deltimple, A. Ghiotto, M. D. Matos, P. Busson","doi":"10.1109/SIRF46766.2020.9040177","DOIUrl":"https://doi.org/10.1109/SIRF46766.2020.9040177","url":null,"abstract":"This paper presents a design methodology for front end module SPDT switches. Then it is applied to an advanced CMOS SOI circuit for Ka-band 5G mobile communications. Firstly the specifications are discussed to address the targeted use case. The chosen technology, offering a simulated FoM of 110 fs, is introduced. Then, the easily scalable non technology dependent design methodology is presented. Measurement results of a series-shunt switch demonstrator are reported for methodology validation. The fabricated SPDT achieves insertion losses lower than 1 dB and an isolation above 20 dB in the 24–31 GHz frequency range. The measured performances are comparable to other recently reported SPDT based on advanced CMOS technologies.","PeriodicalId":221526,"journal":{"name":"2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124100052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
PVT Robust Passive Phase Shifter for 5G MIMO Applications 用于5G MIMO应用的PVT鲁棒无源移相器
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2020-01-01 DOI: 10.1109/SIRF46766.2020.9040176
R. B. Yishay, D. Elad
{"title":"PVT Robust Passive Phase Shifter for 5G MIMO Applications","authors":"R. B. Yishay, D. Elad","doi":"10.1109/SIRF46766.2020.9040176","DOIUrl":"https://doi.org/10.1109/SIRF46766.2020.9040176","url":null,"abstract":"Integrated Ka-Band phase shifter with near-constant insertion-loss for 5G phased array applications is presented in this paper. The differential phase shifter design is based on variable artificial transmission line with digitally tuned inductance and capacitance per unit cell. The IC occupies area of 840 x 840 μm2 and was fabricated in 0.12 μm SiGe BiCMOS process, using CMOS features only. The measured results show insertion loss of 10.2±0.15 dB and phase RMS error of 1.2° at 38.5 GHz with zero power consumption. The phase tuning range is larger than 180 degrees at 37–40 GHz. Excellent PVT robustness is demonstrated over multiple wafer sites, making it suitable for integration in large-scale arrays.","PeriodicalId":221526,"journal":{"name":"2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126868283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
[Ebook cover] (电子书封面)
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2020-01-01 DOI: 10.1109/sirf46766.2020.9040170
{"title":"[Ebook cover]","authors":"","doi":"10.1109/sirf46766.2020.9040170","DOIUrl":"https://doi.org/10.1109/sirf46766.2020.9040170","url":null,"abstract":"","PeriodicalId":221526,"journal":{"name":"2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131373260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-Impedance, Broadband and Compact RMS Detectors for On-Chip Measurements of Millimeter Wave Voltages for Built-In Self-Testing and Debugging 高阻抗、宽带和紧凑型毫米波电压片上测量RMS探测器，用于内置自我测试和调试
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2020-01-01 DOI: 10.1109/SIRF46766.2020.9040184
S. Kshattry, C.K. Yu, C. Wu, Y. Yun, C. Lee, Chong-Yul Cha, W. Choi, N. Preisler, K. O
{"title":"High-Impedance, Broadband and Compact RMS Detectors for On-Chip Measurements of Millimeter Wave Voltages for Built-In Self-Testing and Debugging","authors":"S. Kshattry, C.K. Yu, C. Wu, Y. Yun, C. Lee, Chong-Yul Cha, W. Choi, N. Preisler, K. O","doi":"10.1109/SIRF46766.2020.9040184","DOIUrl":"https://doi.org/10.1109/SIRF46766.2020.9040184","url":null,"abstract":"The high testing cost and challenges of debugging millimeter-wave (mm-wave) CMOS integrated circuits are ameliorated by integrating high-impedance broadband and compact root mean square (RMS) detectors as part of circuits to enable on-chip measurements. The detectors have negligible impact to circuit operation and area, and enable sensing of mm-wave (30 GHz to 300 GHz) voltages using dc/low frequency measurements. The detectors in conjunction with tuning elements can be used to improve circuit performance and yield.","PeriodicalId":221526,"journal":{"name":"2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121874931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Micrometer-Sized Sensors with Free-Space Optical Energy Harvesting in CMOS 微米级CMOS自由空间光能采集传感器
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2020-01-01 DOI: 10.1109/SIRF46766.2020.9040173
Seyed Mohammad Kazem Pour, M. Forghani, A. Babakhani
{"title":"Micrometer-Sized Sensors with Free-Space Optical Energy Harvesting in CMOS","authors":"Seyed Mohammad Kazem Pour, M. Forghani, A. Babakhani","doi":"10.1109/SIRF46766.2020.9040173","DOIUrl":"https://doi.org/10.1109/SIRF46766.2020.9040173","url":null,"abstract":"This paper presents sensor nodes based on optical energy harvesting implemented in commercial CMOS processes. The chips use a photodiode to harvest the optical energy provided through a visible laser directly into a DC power line. This eliminates the need for an analog circuit chain to regulate the harvested power, thereby significantly decreasing chip area. The harvested power is then fed into a digital circuit and an output amplifier. These two parts are multiplexed in time to ensure the most efficient use of the harvested power. The digital circuit converts an 8-bit parallel code into serial and feeds it into the transmitter. The active areas of the implemented chips are 300x60 μm2 and 150x30 μm2.","PeriodicalId":221526,"journal":{"name":"2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130650459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 6.25 mW, +21 dBm OIP3, 0.85 dB NF, 2.5 GHz LNA Employing High Self Gain Device in $0.13 mu mathrm{m}$ SOI Technology 采用高自增益器件的6.25 mW， +21 dBm OIP3, 0.85 dB NF, 2.5 GHz LNA，采用$0.13 mu mathrm{m}$ SOI技术
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2020-01-01 DOI: 10.1109/SIRF46766.2020.9040175
V. Vanukuru, A. Joseph, Anupam Dutta, Balaji Swaminathan, Satyasuresh Choppalli, R. Wolf, M. Jaffe, Yue Tan, Ron Logan, J. Monaghan
{"title":"A 6.25 mW, +21 dBm OIP3, 0.85 dB NF, 2.5 GHz LNA Employing High Self Gain Device in $0.13 mu mathrm{m}$ SOI Technology","authors":"V. Vanukuru, A. Joseph, Anupam Dutta, Balaji Swaminathan, Satyasuresh Choppalli, R. Wolf, M. Jaffe, Yue Tan, Ron Logan, J. Monaghan","doi":"10.1109/SIRF46766.2020.9040175","DOIUrl":"https://doi.org/10.1109/SIRF46766.2020.9040175","url":null,"abstract":"In this paper, significant improvement in cascode LNA performance is demonstrated by using a new high self gain (HSG) common gate (CG) transistor. Emphasis has been on making the output conductance $g_{ds}$ lower and flatter with drain bias. A prototype cascode LNA is designed and fabricated using the developed HSG device in state-of-the-art 0.13 RF SOI technology. Thanks to the HSG device, more than +5 dBm input inter-modulation product (IIP3) improvement is seen in measurements. Very high gain of 19.5 dB at 2.5 GHz with IIP3 value of +1.5 dBm are seen in measurements. Due to optimized transistor sizing, the designed LNA operates at low power of 6.25 mW where 5.2 mA of current is drawn from 1.2 V supply. With integrated high quality factor inductors on high resistivity SOI substrate, the LNA also demonstrates very low noise figure of 0.85 dB. Furthermore, excellent correlation between model simulations and measurements is demonstrated.","PeriodicalId":221526,"journal":{"name":"2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134031020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A two-stage F-band cascode power amplifier with a peak PAE of 17% in SiGe BiCMOS technology SiGe BiCMOS技术中峰值PAE为17%的两级f波段级联功率放大器
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2020-01-01 DOI: 10.1109/SIRF46766.2020.9040172
Vera Kurz, Andrea Bilato, E. Biebl, V. Issakov
{"title":"A two-stage F-band cascode power amplifier with a peak PAE of 17% in SiGe BiCMOS technology","authors":"Vera Kurz, Andrea Bilato, E. Biebl, V. Issakov","doi":"10.1109/SIRF46766.2020.9040172","DOIUrl":"https://doi.org/10.1109/SIRF46766.2020.9040172","url":null,"abstract":"Recently, the requirements in terms of circuit speed have been increasing for many kind of applications and therefore the operating frequencies increase as well. For wireless purposes this comes along with a decreased range, so designing sufficient power amplifier working in the higher frequency band is of particular importance. This paper presents a differential, 2-stage, common-emitter power amplifier with a saturated peak output power of 9 dBm with a 1dB compression point of 8.6 dBm and a peak effiiciency of 17 %, while having a low power consumption of only 95 mW. The actual fabricated power amplifier has its peak amplification at a frequency of 102 GHz. As a highly integrated component it occupies only $560 mu mathrm{m}times 230 mumathrm{m}$ of active chip area.","PeriodicalId":221526,"journal":{"name":"2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122134008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation of Integrated mmW-Downconverter VCOs in SiGe for Offset-PLL FMCW-Transceivers 用于偏置锁相环fmcw收发器的SiGe集成毫米波下变频vco研究
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2020-01-01 DOI: 10.1109/SIRF46766.2020.9040181
C. Bredendiek, K. Aufinger, N. Pohl
{"title":"Investigation of Integrated mmW-Downconverter VCOs in SiGe for Offset-PLL FMCW-Transceivers","authors":"C. Bredendiek, K. Aufinger, N. Pohl","doi":"10.1109/SIRF46766.2020.9040181","DOIUrl":"https://doi.org/10.1109/SIRF46766.2020.9040181","url":null,"abstract":"This paper presents and compares two inherently different LC-VCO architectures for the down-conversion in a offset-PLL. The cross-coupled VCO architecture, which is unpopular in mmW SiGe applications, is compared to the commonly used Colpitts architecture. The two VCOs are fabricated with a supply voltage of 3.3 V in a modern 130 nm SiGe BiCMOS technology with HBTs offering an $f_{mathrm{T}}$ of 250 GHz and $f_{max}$ of 370 GHz. For easier characterization and stabilization in a PLL the same static divide-by-4 chain is added to both VCO chips. The main purpose of this work is the integration of a VCO as a downconverter for a offset-PLL with good phase noise and low power consumption at the same time. At an offset of 1 MHz the Colpitts VCO achieves a phase noise of −108 dBc/Hz at 56 GHz and the cross-coupled VCO achieves a phase noise of −100 dBc/Hz at 68 GHz, respectively. Relative frequency tuning ranges (rFTR) of 26% for the Colpitts type and 43.7% for the cross-coupled VCO are reached.","PeriodicalId":221526,"journal":{"name":"2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115632151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On the Use of Low-Cost Radars and Machine Learning for In-Vehicle Passenger Monitoring 低成本雷达与机器学习在车内乘客监控中的应用
2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2020-01-01 DOI: 10.1109/SIRF46766.2020.9040191
H. Abedi, Shenghang Luo, G. Shaker
{"title":"On the Use of Low-Cost Radars and Machine Learning for In-Vehicle Passenger Monitoring","authors":"H. Abedi, Shenghang Luo, G. Shaker","doi":"10.1109/SIRF46766.2020.9040191","DOIUrl":"https://doi.org/10.1109/SIRF46766.2020.9040191","url":null,"abstract":"In this paper, we use a low-cost low-power mm-wave frequency modulated continuous wave (FMCW) radar for in-vehicle occupant monitoring. We propose an algorithm to identify occupied seats. Instead of using a high-resolution radar which increases the cost and area, we integrate machine learning algorithms with the results of covariance-based angle of arrival estimation Capon beamformer. We apply three classifiers, support vector machine (SVM), K-Nearest Neighbors (KNN) and Random Forest (RF). Our proposed system using SVM classifier achieved 96% accuracy on average in identifying the occupied seats in the test vehicles.","PeriodicalId":221526,"journal":{"name":"2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116796435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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