First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.最新文献_第2页

LOTOS code generation for model checking of STBus based SoC: the STBus interconnection 基于SoC的STBus模型检查的LOTOS代码生成:STBus互连

First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings. Pub Date : 2003-06-24 DOI: 10.1109/MEMCOD.2003.1210105

P. Wodey, Geoffrey Camarroque, Fabrice Baray, R. Hersemeule, Jean-Philippe Cousin

{"title":"LOTOS code generation for model checking of STBus based SoC: the STBus interconnection","authors":"P. Wodey, Geoffrey Camarroque, Fabrice Baray, R. Hersemeule, Jean-Philippe Cousin","doi":"10.1109/MEMCOD.2003.1210105","DOIUrl":"https://doi.org/10.1109/MEMCOD.2003.1210105","url":null,"abstract":"In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stands in validation at the complete system level. At this level, the properties to verify concern the well behavior composed of the different processes interconnected around the system bus. In our work we consider the deadlock-free property. In this paper we present an approach for deadlock detection consisting in generating automatically a LOTOS description of the system. Then, by using CADP toolbox developed at INRIA by the VASY team, the LOTOS description can then be used for the evaluation of temporal logic formula, either on-the-fly or after the generation of a labeled transition system (LTS). The automatic LOTOS code generation is decomposed in two parts, the code generation of the processes behavior (work under progress) and the code generation for the interconnection of processes on a given SoC bus. This paper presents the principles of interconnect abstraction showing that deadlock detection has to take into account properties of the implemented communication channel, avoiding the possibility to build a general deadlock detection tool. The resulting principles are then applied on the STMicroelectronics proprietary SoC bus, the STBus, leading in the development of the LOTOS code generation software.","PeriodicalId":213762,"journal":{"name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117234240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Formal verification of an Intel XScale processor model with scoreboarding, specialized execution pipelines, and impress data-memory exceptions Intel XScale处理器模型的正式验证，包括计分板、专门的执行管道和令人印象深刻的数据内存异常

First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings. Pub Date : 2003-06-24 DOI: 10.1109/MEMCOD.2003.1210090

S. Srinivasan, M. Velev

引用次数: 27

Petri net based interface analysis for fast IP-core integration 基于Petri网的快速ip核集成接口分析

First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings. Pub Date : 2003-06-24 DOI: 10.1109/MEMCOD.2003.1210084

Julio A. de Oliveira Filho, M. Lima, P. Maciel

引用次数: 4

Methods for exploiting SAT solvers in unbounded model checking 利用SAT求解器进行无界模型检验的方法

First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings. Pub Date : 2003-06-24 DOI: 10.1109/MEMCOD.2003.1210098

K. McMillan

引用次数: 9

Finding good counter-examples to aid design verification 寻找好的反例来帮助设计验证

First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings. Pub Date : 2003-06-24 DOI: 10.1109/MEMCOD.2003.1210088

G. Fey, R. Drechsler

引用次数: 20

From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations 从算法和架构规范到分布式实时执行器的自动生成:图形转换的无缝流

First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings. Pub Date : 2003-06-24 DOI: 10.1109/MEMCOD.2003.1210097

T. Grandpierre, Y. Sorel

引用次数: 153

A verification methodology for infinite-state message passing systems 无限状态消息传递系统的验证方法

First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings. Pub Date : 2003-06-24 DOI: 10.1109/MEMCOD.2003.1210110

C. Sprenger, K. Worytkiewicz

引用次数: 2

Real-time property preservation in approximations of timed systems 时间系统近似值中的实时属性保存

First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings. Pub Date : 2003-06-24 DOI: 10.1109/MEMCOD.2003.1210101

Jinfeng Huang, J. Voeten, M. Geilen

引用次数: 46

From use cases to system implementation: statechart based co-design 从用例到系统实现:基于状态图的协同设计

First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings. Pub Date : 2003-06-24 DOI: 10.1109/MEMCOD.2003.1210083

L. Gomes, Anikó Costa

引用次数: 27

Verification of transaction-level SystemC models using RTL testbenches 使用RTL测试台验证事务级SystemC模型

First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings. Pub Date : 2003-06-24 DOI: 10.1109/MEMCOD.2003.1210104

R. Jindal, K. Jain

{"title":"Verification of transaction-level SystemC models using RTL testbenches","authors":"R. Jindal, K. Jain","doi":"10.1109/MEMCOD.2003.1210104","DOIUrl":"https://doi.org/10.1109/MEMCOD.2003.1210104","url":null,"abstract":"System architects working on SoC design have traditionally been hampered by the lack of a coherent methodology for architecture evaluation and co-verification of hardware and software. SystemC 2.0 facilitates the development of transaction-level models (TLMs), which are models of the hardware system components at higher level of abstraction than RTL. Due to lower modeling effort yet higher simulation speed, TLMs are useful for architectural exploration, algorithmic evaluation, hardware-software partitioning and software development. The problems posed by SOC design methodologies require development of models at higher abstraction also for the earlier developed IP's. The development time of a TLM IP is already low, so if we can reduce the verification time by re-use of the earlier RTL test benches we can reduce the overall cost of such an IP TLM. This paper focuses on the methodology to use the RTL testbenches for verification of a SystemC model of the same IP at a higher abstraction level (transaction level), some tools available in the market to support this testbench reuse and the implementation challenges posed by the mentioned verification technique.","PeriodicalId":213762,"journal":{"name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129373408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36