{"title":"PM: A Proof Manager For HOL And Other Provers","authors":"George Fink, M. Archer, Lie Yang","doi":"10.1109/HOL.1991.596295","DOIUrl":"https://doi.org/10.1109/HOL.1991.596295","url":null,"abstract":"Different theorem-proving systems have different things to recommend them: automatic proiiers such as the Boyer-Moore prover or a number of resolution systems minimize human intervention in proving simple first-order assertions, but systems such as HOL or. Nuprl that are based on a more powerful logic better support reasoning about higher abstractions. In typical verification systems, a verifier is limited to the choice of a single theorem-prover. The proof manager PM is intended to allow a verifier to choose among several theorem-proving systems during the course of a single proof. We report on its current status as a HOL interface, and our initial design of a translation scheme that, when possible, transforms HOL input into firstorder assertions suited to the Boyer-Moore prover or automatic first-order provers.","PeriodicalId":213603,"journal":{"name":"1991., International Workshop on the HOL Theorem Proving System and Its Applications","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115402891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Verified Compiler For A Structured Assembly Language","authors":"P. Curzon","doi":"10.1109/HOL.1991.596292","DOIUrl":"https://doi.org/10.1109/HOL.1991.596292","url":null,"abstract":"We describe the verification of a compiler for a subset of the Vista language: a structured assembly language for the Viper microprocessor. This proof has been mechanically checked using the HOL system. We conszder how the compiler correctness theorem could be used to deduce safety and liveness properties of compiled code from theorems stating that these properties hold of the source code. We also show how secwe compilation can be achieved using automated theorem proving techniques.","PeriodicalId":213603,"journal":{"name":"1991., International Workshop on the HOL Theorem Proving System and Its Applications","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130917239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dealing With Temporal Complexity in hardware verification","authors":"J. Herbert","doi":"10.1109/HOL.1991.596267","DOIUrl":"https://doi.org/10.1109/HOL.1991.596267","url":null,"abstract":"An overview of modelling and verifying temporal aspects of digital hGdware behaviour is presented. Varzous techniques can be used for reasoning about temporal behaviour an HOL; here we concentrate on showing that HOL provides a good general basis by describing certain powerful techniques that are well supported by the system. We discuss the embedding of a temporal logic, the use of temporal abstraction to relate diflerent timing levels, and the ability to relate different models of time. Inherent complezity in the lime dependent behaviour of digiial systems is also (lis cussed.","PeriodicalId":213603,"journal":{"name":"1991., International Workshop on the HOL Theorem Proving System and Its Applications","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134241286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Formalization Of VHDL Synthesis Procedure In Higher-order Logic","authors":"X. Wang, E. Stabler","doi":"10.1109/HOL.1991.596278","DOIUrl":"https://doi.org/10.1109/HOL.1991.596278","url":null,"abstract":"VHDL [7] is an IEEE standard hardware description language intended for use in all phases of the creation of electronic systems. LAMBDA [5] is a general-purpose theorem-proving based CAD tool that integrates design and verification. The goal of the research presented in this paper is to provide a linkage between VHDL and LAMBDA, i.e. to synthesize VHDL descriptions using LAMBDA. Our approach is to identify a synthesizable subset of VHDL and define its formal semantics. Based on the semantics defined, a set of semantics equations are derived for each VHDL model. We then translate those semantics equations into a set of equational formulas which are acceptable to LAMBDA as a specification of a design. A library of correctly synthesized components corresponding to most VHDL primitive operators is also established. Those components are used as building blocks during synthesis.","PeriodicalId":213603,"journal":{"name":"1991., International Workshop on the HOL Theorem Proving System and Its Applications","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133470315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Formal Hardware Verification In Hol And In Boyer-moore: A Comparative Analysis","authors":"C. M. Angelo, D. Verkest, L. Claesen, H. Man","doi":"10.1109/HOL.1991.596298","DOIUrl":"https://doi.org/10.1109/HOL.1991.596298","url":null,"abstract":"Different types of problems in the hardware verification field have inspired different methodologies to tackle them. When different approaches can verify the same class of circuits, at a given level of abstraction, it is often the case that each one has advantages and drawbacks with respect to the others. Comparing different methodologies is important, not only to identify the right tool for the right task, but also to evaluate the compromises of different approaches. This paper summarises a comparison between the theorem proving environments HOL and Boyer-Moore, based on a practical experience with both systems for the verification of a parameterised module from the CATHE DRAL Silicon Compiler library.","PeriodicalId":213603,"journal":{"name":"1991., International Workshop on the HOL Theorem Proving System and Its Applications","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125164145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Learning To Use HOL","authors":"P. Loewenstein","doi":"10.1109/HOL.1991.596274","DOIUrl":"https://doi.org/10.1109/HOL.1991.596274","url":null,"abstract":"Four years attemting to use a theorem prover for hardware design has taught much. The initial difficulty of coping with an unfriendly system, through some initial simple examples to more complex examples has generated frustration, enlightenment, boredom and occasional triumph. This paper looks at these experiences and draws conclusions about what is feasible now, and what needs to be done to make theorem proving a viable verification technique for real systems.","PeriodicalId":213603,"journal":{"name":"1991., International Workshop on the HOL Theorem Proving System and Its Applications","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130081505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design Choices In Specification Languages And Verification Systems","authors":"J. Rushby","doi":"10.1109/HOL.1991.596287","DOIUrl":"https://doi.org/10.1109/HOL.1991.596287","url":null,"abstract":"We describe some of the design choices that should be considered in the development and application of specification languages and verification systems. A principal issue is the need to reconcile the desire for expressiveness in the specification language with the ability to provide effective mechanical support. We argue that this reconciliation is assisted by a novel approach to specification language design that requires theorem proving to be used during typechecking. A second key requirement is for the theorem prover to be specialized towards the needs of verification. This means that the theorem prover must assist in the rapid identification of the sources of errors in incorrect theorems as well as in the certification of true theorems, and that it must produce a proof suitable for human review. We argue that a combination of powerful automation (including decision procedures) at the low level, and user-guidance at the high level, provides ihe most efledive approach to these goals.","PeriodicalId":213603,"journal":{"name":"1991., International Workshop on the HOL Theorem Proving System and Its Applications","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124420341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Need For Formal Verification In Hardware Design And What Formal Verification Has Not Done For Me Lately","authors":"K. Keutzer","doi":"10.1109/HOL.1991.596275","DOIUrl":"https://doi.org/10.1109/HOL.1991.596275","url":null,"abstract":"The problem of verifying that the design of an integrated circuit will perform the tasks required by its specification is currently a perplexing one for circuit designers. Unfortunately, formal verification techniques in general, and theorem proving techniques in particular, have not been able to alleviate this problem. This paper briefly outlines the verification tasks required in a circuit design and identify those verification tasks for which formal approaches may be most beneficial.","PeriodicalId":213603,"journal":{"name":"1991., International Workshop on the HOL Theorem Proving System and Its Applications","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132187668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Verification Of Integrated Subsystems","authors":"E. T. Schubert","doi":"10.1109/HOL.1991.596270","DOIUrl":"https://doi.org/10.1109/HOL.1991.596270","url":null,"abstract":"based on an AMD chip. e An interrupt controller based on the Intel 8259A controller chip. Our main emphasis is on the verification of “real” systems. It is hoped that the outcome of this work will be a convincing demonstration of the feasibility of applying verification to a large class of practical systems. In addition, through the examples being verified, we are confronting problems in applying mechanical verification methods to large systems that are suggestive e A DMA controller, based on the Intel 8237A. e A floating point co-processor whose specification is the IEEE floating standard, based on Motorola MC68881. e A memory management unit based on a Motorola design.","PeriodicalId":213603,"journal":{"name":"1991., International Workshop on the HOL Theorem Proving System and Its Applications","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130998130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Using HOL To Produce Custom Verification Tools","authors":"D. Shepherd","doi":"10.1109/HOL.1991.596283","DOIUrl":"https://doi.org/10.1109/HOL.1991.596283","url":null,"abstract":"HOL is a general purpose verification tool and as such has been applied to many verification problems. However, due to its generality it is not as eficient as a specially written tool would be. This paper demonstrates how HOL can be used to generate a special purpose tool whose correctness has been established through proof. This is shown through an example of some work pelformed as part of the IMS T9000 design and explains how this could be turn, with improvements, into a more general technique. It should be understood that this paper does not set out to demonstrate a method for verifying ROM compaction but uses this task as an illustration of a potential technique for developing secure special purpose tools.","PeriodicalId":213603,"journal":{"name":"1991., International Workshop on the HOL Theorem Proving System and Its Applications","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128935883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}