Formalization Of VHDL Synthesis Procedure In Higher-order Logic

Abstract

VHDL [7] is an IEEE standard hardware description language intended for use in all phases of the creation of electronic systems. LAMBDA [5] is a general-purpose theorem-proving based CAD tool that integrates design and verification. The goal of the research presented in this paper is to provide a linkage between VHDL and LAMBDA, i.e. to synthesize VHDL descriptions using LAMBDA. Our approach is to identify a synthesizable subset of VHDL and define its formal semantics. Based on the semantics defined, a set of semantics equations are derived for each VHDL model. We then translate those semantics equations into a set of equational formulas which are acceptable to LAMBDA as a specification of a design. A library of correctly synthesized components corresponding to most VHDL primitive operators is also established. Those components are used as building blocks during synthesis.