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Exploiting the reconfigurability of the PAnDA architecture to overcome physical substrate variations 利用PAnDA架构的可重构性来克服物理基板的变化
2013 IEEE International Conference on Evolvable Systems (ICES) Pub Date : 2013-04-16 DOI: 10.1109/ICES.2013.6613280
James Alfred Walker, M. Trefzer, S. Bale, A. Tyrrell
{"title":"Exploiting the reconfigurability of the PAnDA architecture to overcome physical substrate variations","authors":"James Alfred Walker, M. Trefzer, S. Bale, A. Tyrrell","doi":"10.1109/ICES.2013.6613280","DOIUrl":"https://doi.org/10.1109/ICES.2013.6613280","url":null,"abstract":"Field programmable gate arrays (FPGAs) are widely used in applications where on-line reconfigurable signal processing is required. Speed and function density of FPGAs are increasing as transistor sizes shrink to the nano-scale. As these transistors reduce in size, intrinsic variability becomes more of a problem, as every physical instance of a design behaves differently, resulting in a decrease in fabrication yield. This paper describes an adaptive, evolvable architecture that allows for correction and optimisation of circuits directly in hardware using bio-inspired techniques. Similar to FPGAs, the programmable analogue and digital array (PAnDA) architecture introduced here can be reconfigured on a digital level for circuit design. Accessing additional configuration options of the underlying analogue level enables continuous adjustment of circuit characteristics at run-time, which enables dynamic optimisation of the mapped design's performance. Moreover, the yield of devices can be improved post-fabrication via reconfiguration at the analogue level, which can overcome faults caused by variability and process defects.","PeriodicalId":213522,"journal":{"name":"2013 IEEE International Conference on Evolvable Systems (ICES)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126849879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Towards evolvable systems based on the Xilinx Zynq platform 迈向基于赛灵思Zynq平台的可进化系统
2013 IEEE International Conference on Evolvable Systems (ICES) Pub Date : 2013-04-16 DOI: 10.1109/ICES.2013.6613287
R. Dobai, L. Sekanina
{"title":"Towards evolvable systems based on the Xilinx Zynq platform","authors":"R. Dobai, L. Sekanina","doi":"10.1109/ICES.2013.6613287","DOIUrl":"https://doi.org/10.1109/ICES.2013.6613287","url":null,"abstract":"Field programmable gate arrays (FPGAs) are considered as a good platform for digital evolvable hardware systems. Researchers introduced virtual reconfigurable circuits as the response to the insufficient support of partial reconfiguration in early FPGAs. Later, the features of FPGAs allowed the designers to develop evolvable systems fully exploiting native reconfiguration infrastructures. Xilinx recently introduced a new platform called Zynq-7000 all programmable (AP) system-on-chip (SoC) which has the potential to become the next revolutionary step in evolvable hardware design. The paper analyzes Zynq-7000 AP SoC from the perspective of an evolvable hardware designer. Several scenarios are described of how to implement evolvable systems on a developmental board equipped with this programmable SoC. These scenarios are evaluated in terms of area overhead, execution time, reconfiguration time and throughput. The resulting observations should be useful for those who are going to develop real-world evolvable systems on the Zynq-7000 AP SoC platform.","PeriodicalId":213522,"journal":{"name":"2013 IEEE International Conference on Evolvable Systems (ICES)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126543687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Investigating evolvable hardware classification for the BioSleeve electromyographic interface 研究生物袖肌电图界面的可进化硬件分类
2013 IEEE International Conference on Evolvable Systems (ICES) Pub Date : 2013-04-16 DOI: 10.1109/ICES.2013.6613285
K. Glette, Paul Kaufmann, C. Assad, Michael T. Wolf
{"title":"Investigating evolvable hardware classification for the BioSleeve electromyographic interface","authors":"K. Glette, Paul Kaufmann, C. Assad, Michael T. Wolf","doi":"10.1109/ICES.2013.6613285","DOIUrl":"https://doi.org/10.1109/ICES.2013.6613285","url":null,"abstract":"We investigate the applicability of an evolvable hardware classifier architecture for electromyography (EMG) data from the BioSleeve wearable human-machine interface, with the goal of having embedded training and classification. We investigate classification accuracy for datasets with 17 and 11 gestures and compare to results of Support Vector Machines (SVM) and Random Forest classifiers. Classification accuracies are 91.5% for 17 gestures and 94.4% for 11 gestures. Initial results for a field programmable array (FPGA) implementation of the classifier architecture are reported, showing that the classifier architecture fits in a Xilinx XC6SLX45 FPGA. We also investigate a bagging-inspired approach for training the individual components of the classifier with a subset of the full training data. While showing some improvement in classification accuracy, it also proves useful for reducing the number of training instances and thus reducing the training time for the classifier.","PeriodicalId":213522,"journal":{"name":"2013 IEEE International Conference on Evolvable Systems (ICES)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131209272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Approximate circuit design by means of evolvable hardware 采用可进化硬件进行近似电路设计
2013 IEEE International Conference on Evolvable Systems (ICES) Pub Date : 2013-04-16 DOI: 10.1109/ICES.2013.6613278
L. Sekanina, Z. Vašíček
{"title":"Approximate circuit design by means of evolvable hardware","authors":"L. Sekanina, Z. Vašíček","doi":"10.1109/ICES.2013.6613278","DOIUrl":"https://doi.org/10.1109/ICES.2013.6613278","url":null,"abstract":"This paper deals with evolutionary design of approximate circuits. This class of circuits is characterized by relaxing the requirement on functional equivalence between the specification and implementation in order to reduce the area on a chip or minimize energy consumption. We proposed a CGP-based automated design method which enables to find a good trade off between key circuit parameters (functionality, area and power consumption). In particular, the digital approximate circuits consisting of elementary gates are addressed in this paper. Experimental results are provided for combinational single-output circuits and adders where two different metrics are compared for the error assessment.","PeriodicalId":213522,"journal":{"name":"2013 IEEE International Conference on Evolvable Systems (ICES)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127433011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
Using evolved controllers to adapt behavior in autonomous nonlinear systems 采用进化控制器自适应自主非线性系统的行为
2013 IEEE International Conference on Evolvable Systems (ICES) Pub Date : 2013-04-16 DOI: 10.1109/ICES.2013.6613275
G. Greenwood, Shubham Chopra
{"title":"Using evolved controllers to adapt behavior in autonomous nonlinear systems","authors":"G. Greenwood, Shubham Chopra","doi":"10.1109/ICES.2013.6613275","DOIUrl":"https://doi.org/10.1109/ICES.2013.6613275","url":null,"abstract":"The proportional-integrative-derivative (PID) controller provides effective control in linear systems. However, performance is poor in nonlinear systems unless combined with a fuzzy logic controller (FLC) that modifies the PID controller gains as needed. System behavior can adapt to operational environment changes by switching different FLCs online. But that capability requires accurate operational environment identification. In autonomous systems identification must be done without significant human presence. This paper describes how Discrete Fourier Transforms can identify operational environments in an autonomous nonlinear system, which in this work is a DC motor. Simulation results shows the proposed method accurately identifies the physical environment and altering the FLC online correctly adapts the system's behavior.","PeriodicalId":213522,"journal":{"name":"2013 IEEE International Conference on Evolvable Systems (ICES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129176915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Extending the hardware architecture of systemic computation to a complete programming platform 将系统计算的硬件架构扩展为一个完整的编程平台
2013 IEEE International Conference on Evolvable Systems (ICES) Pub Date : 2013-04-16 DOI: 10.1109/ICES.2013.6613282
C. Sakellariou, P. Bentley
{"title":"Extending the hardware architecture of systemic computation to a complete programming platform","authors":"C. Sakellariou, P. Bentley","doi":"10.1109/ICES.2013.6613282","DOIUrl":"https://doi.org/10.1109/ICES.2013.6613282","url":null,"abstract":"Systemic Computation is an unconventional paradigm which defines a model of natural behavior and implies a massively parallel computer architecture. It is designed to be a computational paradigm for natural systems and processes modeling. Existing software implementations have been too limited in terms of performance, flexibility and programmability. This paper solves key problems that remained in earlier work, introduced towards the first practical hardware Systemic Computation implementation using FPGAs. This is achieved by making various optimizations and software additions, resulting in a complete and efficient SC programming platform.","PeriodicalId":213522,"journal":{"name":"2013 IEEE International Conference on Evolvable Systems (ICES)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122833992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Concurrent evolution of hardware and software for application-specific microprogrammed systems 针对特定应用的微程序系统的硬件和软件的并行发展
2013 IEEE International Conference on Evolvable Systems (ICES) Pub Date : 2013-04-16 DOI: 10.1109/ICES.2013.6613281
M. Minarik, L. Sekanina
{"title":"Concurrent evolution of hardware and software for application-specific microprogrammed systems","authors":"M. Minarik, L. Sekanina","doi":"10.1109/ICES.2013.6613281","DOIUrl":"https://doi.org/10.1109/ICES.2013.6613281","url":null,"abstract":"Embedded systems often have to calculate some mathematical functions using iterative algorithms. When hard constraints are specified in terms of the area on the chip a possible solution is to implement the iterative algorithm by means of a microprogrammed digital circuit. In this paper, the first version of a new design framework is presented to automate the design and optimization of such microprogrammed systems. The framework utilizes evolutionary design and optimization techniques to find the most suitable implementation of the hardware architecture as well as the program for the programmable logic controller. The functionality of the proposed approach is evaluated using evolutionary design of three HW/SW systems under different constraints.","PeriodicalId":213522,"journal":{"name":"2013 IEEE International Conference on Evolvable Systems (ICES)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131713011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Body building: Hatching robot organisms 健身:孵化机器人有机体
2013 IEEE International Conference on Evolvable Systems (ICES) Pub Date : 2013-04-16 DOI: 10.1109/ICES.2013.6613277
Berend Weel, E. Haasdijk, A. Eiben
{"title":"Body building: Hatching robot organisms","authors":"Berend Weel, E. Haasdijk, A. Eiben","doi":"10.1109/ICES.2013.6613277","DOIUrl":"https://doi.org/10.1109/ICES.2013.6613277","url":null,"abstract":"We propose a new scenario for the evolution of robot morphologies based on an egg metaphor. A swarm of robots is released in a large arena in which they form organisms through a process of morphogenesis. These organisms can reproduce by fertilising eggs in their vicinity, these fertilised eggs in turn build new organisms by recruiting free modules as a `seed'. We investigate the influence of three parameters of this evolutionary system: the time eggs wait to be fertilised, the maximum time a seed can use to recruit modules to form an organism and how long an organism lives. Specifically we investigate the influence of these parameters on the size and stability of the population of eggs, seeds and organisms. It is shown that the influence of the lifetime of an organism is the largest, and leads to many organisms, it should be set much higher than the other two. Furthermore setting the time an egg can be fertilised and the maximum time a seed is allowed to build an organism to the same value results in the most stable system regarding number of eggs and seeds. Finally setting the maximum seed time higher leads to to a slightly smaller population of bigger organisms.","PeriodicalId":213522,"journal":{"name":"2013 IEEE International Conference on Evolvable Systems (ICES)","volume":"536 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127642801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On the implications of plug-and-learn adaptive hardware components toward a cyberphysical systems perspective on evolvable and adaptive hardware 关于即插即用的自适应硬件组件对可进化和自适应硬件的网络物理系统观点的影响
2013 IEEE International Conference on Evolvable Systems (ICES) Pub Date : 2013-04-16 DOI: 10.1109/ICES.2013.6613283
J. Gallagher, E. Matson, G. Greenwood
{"title":"On the implications of plug-and-learn adaptive hardware components toward a cyberphysical systems perspective on evolvable and adaptive hardware","authors":"J. Gallagher, E. Matson, G. Greenwood","doi":"10.1109/ICES.2013.6613283","DOIUrl":"https://doi.org/10.1109/ICES.2013.6613283","url":null,"abstract":"Evolvable and Adaptive Hardware (EAH) Systems have been a subject of study for about two decades. This paper argues that viewing EAH devices in isolation from the larger systems in which they serve as components is somewhat dangerous in that EAH devices can subvert the design hierarchies upon which designers base verification and validation efforts. The paper proposes augmenting EAH components with additional machinery to enable the application of model-checking and related Cyber-Physical Systems techniques to extract evolving intra-module relationships for formal verification and validation purposes.","PeriodicalId":213522,"journal":{"name":"2013 IEEE International Conference on Evolvable Systems (ICES)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132816598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Evolutionary design of a wide-band twisted dipole antenna for X-band application x波段宽带扭曲偶极子天线的进化设计
2013 IEEE International Conference on Evolvable Systems (ICES) Pub Date : 2013-04-16 DOI: 10.1109/ICES.2013.6613276
Zhu Liu, Sanyou Zeng, Yuhong Jiang, Changhe Li, Ni Ouyang
{"title":"Evolutionary design of a wide-band twisted dipole antenna for X-band application","authors":"Zhu Liu, Sanyou Zeng, Yuhong Jiang, Changhe Li, Ni Ouyang","doi":"10.1109/ICES.2013.6613276","DOIUrl":"https://doi.org/10.1109/ICES.2013.6613276","url":null,"abstract":"A novel dipole antenna at X-band with wide-band operation is presented in this paper. A wire structure model with two centrosymmetric arms used for evolutionary design is proposed, which can be encoded using a vector of real-valued parameters for evolutionary algorithms to optimize. Differential evolution is used to solve the antenna problem, and the results we get show good performance: bandwidth larger than 4.5GHz and peak gain above 8dBi over the bandwidth. Compared with the antenna designed by a state-of-the-art conventional method we referenced, which has a bandwidth about 2.5GHz with peak gain around 7dBi, the evolved antenna shows significant improvements.","PeriodicalId":213522,"journal":{"name":"2013 IEEE International Conference on Evolvable Systems (ICES)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133252816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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