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[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit最新文献

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ASIC technologies ASIC技术
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 2022-09-21 DOI: 10.1109/ASIC.1992.270298
M.J.S. Smith
{"title":"ASIC technologies","authors":"M.J.S. Smith","doi":"10.1109/ASIC.1992.270298","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270298","url":null,"abstract":"The physical differences between currently available ASIC technologies are reported with emphasis on field-programmable gate arrays. Two factors affecting the choice of ASIC technology (costs and the importance of synthesis) are discussed. It is shown that the use of synthesis techniques can make as much difference in the performance of a system as a change in technology. The ability to use synthesis techniques effectively is an important criterion in selecting an ASIC technology.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133338535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Results of a topologically partitioned parallel automatic test pattern generation system on a distributed-memory multiprocessor 分布式存储多处理器上拓扑分区并行自动测试模式生成系统的结果
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270264
R. Bell, R. Klenke, J. Aylor, R.D. Williams
{"title":"Results of a topologically partitioned parallel automatic test pattern generation system on a distributed-memory multiprocessor","authors":"R. Bell, R. Klenke, J. Aylor, R.D. Williams","doi":"10.1109/ASIC.1992.270264","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270264","url":null,"abstract":"The design and implementation of an object-oriented topologically partitioned parallel automatic test pattern generation (ATPG) system, ES-TPS, on a multiple-instruction multiple-data (MIMD) distributed-memory multiprocessor are described. The ATPG system is based upon the D-algorithm and performs test generation on a circuit which has been topologically partitioned across several processors. Fault partitioning and algorithmic parallelizations are included in the system to attempt to achieve speedup.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123172143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A universal single chip analog CMOS speech processor for analog mobile cellular phones 通用单片模拟CMOS语音处理器，用于模拟移动蜂窝电话
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270260
M. Gronroos, J. Polonen, P. Vakiparta
{"title":"A universal single chip analog CMOS speech processor for analog mobile cellular phones","authors":"M. Gronroos, J. Polonen, P. Vakiparta","doi":"10.1109/ASIC.1992.270260","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270260","url":null,"abstract":"A single-chip analog CMOS speech processor for advanced mobile-phone system (AMPS), total access communication system (TACS), NMT900, and NMT450 mobile cellular phones is represented. The circuit includes all necessary speech processing functions including compressor, expander, and deviation limiters. It includes a multi-frequency generator and buzzer driver for DTMF and general purpose signaling. The circuit is integrated in a standard 2- mu m CMOS double-poly double-metal process and requires 32.8 mm/sup 2/.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124812786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Transmission line models of multi-chip module interconnects 多芯片模块互连的传输线模型
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270246
G. R. Ellis, P. R. Mukund
{"title":"Transmission line models of multi-chip module interconnects","authors":"G. R. Ellis, P. R. Mukund","doi":"10.1109/ASIC.1992.270246","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270246","url":null,"abstract":"An overview of the important transmission line properties of circuit interconnects is given, and it is shown how these properties can affect the operation of high speed and high density multichip modules (MCMs). Both frequency and time domain issues are addressed. The effects of line-caused delay and signal noise on MCM layouts are reported.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"NS28 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116552579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High performance DSP ASIC for multiply, divide and square root 高性能DSP专用集成电路的乘，除和平方根
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270275
Roger Francis Woods, S. E. McQuillan, J. Dowling, J. McCanny
{"title":"High performance DSP ASIC for multiply, divide and square root","authors":"Roger Francis Woods, S. E. McQuillan, J. Dowling, J. McCanny","doi":"10.1109/ASIC.1992.270275","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270275","url":null,"abstract":"The design of a high-speed ASIC that combines the operations of multiplication, division and square root is described. The chip is based on a systolic array architecture that uses a redundant number system and allows multiplication, division, and square root to be combined on the same hardware. The chip has been designed using a 1.5- mu m, double-metal CMOS technology, operates on 16-b sign magnitude data, and has a throughput rate of 40 Msample/s for each operation.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128427228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Comprehensive structural testing of ASIC macrocells, a comparative analysis 综合ASIC巨细胞结构测试，对比分析
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270290
H. Sucar
{"title":"Comprehensive structural testing of ASIC macrocells, a comparative analysis","authors":"H. Sucar","doi":"10.1109/ASIC.1992.270290","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270290","url":null,"abstract":"A comparative analysis of three test generation methods for designs based on CMOS ASIC macrocells is presented. These methods are (1) stuck-at tests, (2) IDDQ tests; and (3) crosscheck tests. The fault modeling technique for each method is described. The test generated by using the fault model of each method is used to compare the completeness of the methods in terms of actual defect coverage. Conclusions are derived for each method according to its effectiveness for achieving desired quality levels.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128767161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An 8-10-bit, 1-40 MHz analog signal processor with configurable performance for electronic imaging applications 8-10位，1-40 MHz模拟信号处理器，具有可配置的性能，适用于电子成像应用
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270261
D. Boisvert, M.J. Gaboury, R. B. Lloyd
{"title":"An 8-10-bit, 1-40 MHz analog signal processor with configurable performance for electronic imaging applications","authors":"D. Boisvert, M.J. Gaboury, R. B. Lloyd","doi":"10.1109/ASIC.1992.270261","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270261","url":null,"abstract":"An 8-10-b, 1-40-MHz analog signal processing ASIC that performs correlated double sampling (CDS), variable gain adjustment, periodic DC restoration, analog inversion, and analog multiplexing for black level insertion or synchronization is described. The ASIC has been developed in a configurable bipolar analog array for electronic imaging applications and is optimized for image sensor output rates of 1-40 MHz by varying only four process masks. In one configuration, suitable for HDTV camera systems, the ASIC operates at over 38 MHz with S/N, linearity, and temperature stability of over 8 b. In a second configuration, suitable for many high quality electronic imaging applications, the ASIC operates at over 15 MHz with S/N, linearity, and temperature stability of over 10 b.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129047336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 1.2 mu m CMOS differential I/O system capable of 400 Mbps transmission rates 1.2 μ m CMOS差分I/O系统，传输速率400mbps
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270254
W.G. Rivard, M.J.S. Smith, G. Stone, D. James
{"title":"A 1.2 mu m CMOS differential I/O system capable of 400 Mbps transmission rates","authors":"W.G. Rivard, M.J.S. Smith, G. Stone, D. James","doi":"10.1109/ASIC.1992.270254","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270254","url":null,"abstract":"High-bandwidth processor-to-processor connections, like the IEEE Std. 1596 scalable coherent interface (SCI), are being proposed as functional replacements for computer-system buses. To be cost-effective, it is important to drive the SCI links directly from CMOS VLSI components. To meet this need, a low-power, low-voltage-swing CMOS differential I/O driver/receiver system has been developed and is described. Measured results demonstrate 400-Mbps switching speeds using 1.2- mu m CMOS technology.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124665559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A CMOS ASIC for real time microwave spectral estimation applications 一种用于实时微波频谱估计的CMOS专用集成电路
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270305
R. Siferd, S. Perumal, W. McCormick
{"title":"A CMOS ASIC for real time microwave spectral estimation applications","authors":"R. Siferd, S. Perumal, W. McCormick","doi":"10.1109/ASIC.1992.270305","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270305","url":null,"abstract":"The design, simulation, and testing results of a CMOS ASIC are presented for mapping the outputs of multiple instantaneous frequency measurement correlation to a spectral estimation of the center frequency of submicrosecond pulses in real time. Preliminary testing indicated fully functional designs.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124056233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Image processing ASIC for real-time contrast enhancement 用于实时对比度增强的图像处理ASIC
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270278
Yong-Chul Shin, R. Sridhar, V. Demjanenko, P. W. Palumbo, J. Hull, S. Srihari
{"title":"Image processing ASIC for real-time contrast enhancement","authors":"Yong-Chul Shin, R. Sridhar, V. Demjanenko, P. W. Palumbo, J. Hull, S. Srihari","doi":"10.1109/ASIC.1992.270278","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270278","url":null,"abstract":"An ASIC chip set that implements adaptive local contrast enhancement for real-time image processing is presented. The contrast enhancement is based on a nonlinear mapping M(A, sigma ,P), where A is an average, sigma is a standard deviation, and P is a center pixel over a 9*9 window. The throughput rate is 100 ns per pixel. A dynamic programming technique and pipelining are used to minimize the space-time constraint in the implementation.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126531189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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