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[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit最新文献

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A low-voltage metal-programmable SRAM compiler for gate array 用于门阵列的低压金属可编程SRAM编译器
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270210
F. Svejda, R.S. Tupuri, S. Madhuri, R. Rath
{"title":"A low-voltage metal-programmable SRAM compiler for gate array","authors":"F. Svejda, R.S. Tupuri, S. Madhuri, R. Rath","doi":"10.1109/ASIC.1992.270210","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270210","url":null,"abstract":"A faster and more area efficient metal-programmable SRAM compiler for a 3.3 V 0.65 mu m effective CMOS sea-of-gates (SOG) array has been designed. A base cell, optimized for memory, features reduced bit and word-line parasitics in order to improve speed and provide high density SRAMs for ASIC applications.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134062657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An analog parallel processor for the dynamic programming paradigm 一个模拟并行处理器的动态规划范例
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270200
K. Soumyanath, J. V. Von Arx
{"title":"An analog parallel processor for the dynamic programming paradigm","authors":"K. Soumyanath, J. V. Von Arx","doi":"10.1109/ASIC.1992.270200","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270200","url":null,"abstract":"A novel analog parallel approach to the implementation of the dynamic programming paradigm is described. The approach has been used to design a test chip which solves the single source, shortest path problem in a fully connected eight-mode network. The distributed processor design has been fabricated in a 2- mu m double poly low noise CMOS process using a die area of 2.22*2.22 mils. The design has a typical setting time of 100 ns and a worst case power dissipation of 3.5 W.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132835979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Distributed automatic test pattern generation 分布式自动测试模式生成
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270263
T. Chan
{"title":"Distributed automatic test pattern generation","authors":"T. Chan","doi":"10.1109/ASIC.1992.270263","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270263","url":null,"abstract":"An automatic test pattern generation (ATPG) program which can partition the logic and stuck-at faults of any scan-based ASIC into disjoint sets is described. These logic partitions and fault sets are processed concurrently over a computing network. The performance of the ATPG is improved significantly, and it can handle very large ASICs.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126588629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Electrical performance analysis of packaged CMOS ASIC devices and systems 封装的CMOS ASIC器件和系统的电气性能分析
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270272
R. Senthinathan, J. Prince
{"title":"Electrical performance analysis of packaged CMOS ASIC devices and systems","authors":"R. Senthinathan, J. Prince","doi":"10.1109/ASIC.1992.270272","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270272","url":null,"abstract":"The performance of scaled and packaged CMOS devices is analyzed. A detailed investigation of methods of calculating simultaneous switching noise, including negative feedback influence, is performed. Equivalent chip-package interface circuits and closed-form equations are included. A method of modeling L/sub eff/ as seen by the output driver circuit on its V/sub DD//V/sub SS/ path is investigated. Application specific output driver circuits are designed to minimize effective simultaneous switching noise. The performance and noise characteristics of such drivers are compared with those of conventional output drivers.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132991039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Behavioural VHDL code generation for synchronous FSMs 同步FSMs的行为VHDL代码生成
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270206
X.J. Wang, S.R.W. Grainger, A. Cooper
{"title":"Behavioural VHDL code generation for synchronous FSMs","authors":"X.J. Wang, S.R.W. Grainger, A. Cooper","doi":"10.1109/ASIC.1992.270206","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270206","url":null,"abstract":"An interactive system, HLSS, that generates behavioral VHDL (VHSIC Hardware Description Language) code for synchronous finite state machines (FSMs) is described. A process model graph that separates the combinational and sequential logic elements in a FSM is used in code generation. The generated code can be used for synthesis as well as simulation. A complete example is given.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129437052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Embedded 6 bit flash converter design for digital stereo sound decoder 嵌入式6位flash转换器的数字立体声解码器设计
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270262
V. Pathak, K. Ritchie, M. Kitchin
{"title":"Embedded 6 bit flash converter design for digital stereo sound decoder","authors":"V. Pathak, K. Ritchie, M. Kitchin","doi":"10.1109/ASIC.1992.270262","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270262","url":null,"abstract":"The design of a 25-MHz, 6-b flash converter embedded in a customized digital signal processor for decoding of digital stereo sound broadcast on terrestrial TV channels is described. The design is based upon an offset cancellation comparator which obviates the need for large storage capacitors traditionally used for input offset reduction, and makes the design easier to fabricate in standard CMOS technology. Simple measurement techniques used for design debug are described.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128617326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Layout synthesis of combinational blocks from behavioral hardware descriptions 从行为硬件描述中合成组合块的布局
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270311
Q. Wu, S. Ramirez-Chavez
{"title":"Layout synthesis of combinational blocks from behavioral hardware descriptions","authors":"Q. Wu, S. Ramirez-Chavez","doi":"10.1109/ASIC.1992.270311","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270311","url":null,"abstract":"A CAD tool that generates the layout of a combinational circuit from a behavioral hardware description language (HDL) representation is presented. A minimized transistor netlist is synthesised. Simulated annealing is used to determine the optimal placement and routing of each transistor group. As input, the system accepts VHSIC hardware description language (VHDL), VERILOG, truth table, and Boolean equation descriptions. For simulation purposes SPICE models of the circuit are also generated.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131019170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Micro data flow 微数据流
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270230
S.-L.L. Lu, L. Merani
{"title":"Micro data flow","authors":"S.-L.L. Lu, L. Merani","doi":"10.1109/ASIC.1992.270230","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270230","url":null,"abstract":"Digital computation systems based on transition signal framework have many advantages. The synthesis of a self-timed physical design from a high-level dataflow specification is examined. The approach maps tokens that travel on data and control arcs of a dataflow graph into transitions of the event signals. The two-phase event signal transition style is employed, where both the rising edge and the trailing edge may represent the arrival of a token. The detailed designs of all seven primitives of a dataflow graph are presented.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126739315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Evaluation of test strategies for multichip modules 多芯片模块测试策略的评估
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270269
T. Lin, J. Comito, C. Kaseff
{"title":"Evaluation of test strategies for multichip modules","authors":"T. Lin, J. Comito, C. Kaseff","doi":"10.1109/ASIC.1992.270269","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270269","url":null,"abstract":"Two parallel testing strategies for multichip modules-the boundary-scan technique and the cascadable built-in tester (CBIT)-are evaluated in terms of testing time, fault coverage, and area overhead. Results on a small-scale processor configuration favor the CBIT design for test effectiveness of the chip, and the boundary-scan design for area overhead interconnection tests.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"56 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114085544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Early wirability checking and 2D congestion-driven circuit placement 早期连接性检查和2D拥塞驱动电路的放置
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit Pub Date : 1992-09-21 DOI: 10.1109/ASIC.1992.270308
R. Tsay, S. Chang, J. Thorvaldson
{"title":"Early wirability checking and 2D congestion-driven circuit placement","authors":"R. Tsay, S. Chang, J. Thorvaldson","doi":"10.1109/ASIC.1992.270308","DOIUrl":"https://doi.org/10.1109/ASIC.1992.270308","url":null,"abstract":"An effective congestion-driven placement algorithm that uses initial global routing model for congestion analysis and optimization is proposed. The approach has been used for rescuing many difficult chip designs when intensive rip-up and remote technique could not complete the wiring. It is demonstrated that the congestion cost evaluation step of the algorithm can be used as an accurate early wirability checking utility.<<ETX>>","PeriodicalId":211702,"journal":{"name":"[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit","volume":"637 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131880411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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