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2006 IEEE Workshops on Computers in Power Electronics最新文献

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Input Impedance Modeling of Line-Frequency Rectifiers by the Method of Impedance Mapping 基于阻抗映射法的线频整流器输入阻抗建模
2006 IEEE Workshops on Computers in Power Electronics Pub Date : 2006-07-16 DOI: 10.1109/COMPEL.2006.305654
J. Sun, J. Colon, K. Karimi
{"title":"Input Impedance Modeling of Line-Frequency Rectifiers by the Method of Impedance Mapping","authors":"J. Sun, J. Colon, K. Karimi","doi":"10.1109/COMPEL.2006.305654","DOIUrl":"https://doi.org/10.1109/COMPEL.2006.305654","url":null,"abstract":"This paper presents a systematic method for modeling small-signal input impedance of line-frequency AC-DC converters. The objective is to develop proper models that can be used for stability analysis of AC power systems with significant DC loads powered by such converters. The proposed modeling method uses harmonic linearization and Fourier analysis techniques to describe the current and voltage mapping process through the converter switching circuit. The voltage and current mapping relations are then combined to give an impedance mapping model which converts the impedance of any circuit or system connected to the DC output of converter into a corresponding small-signal input impedance of the converter at the AC side. Similar relations can be used to map the AC source impedance into the DC side to give the equivalent DC source impedance for stability analysis of the DC subsystem. This paper focuses on the basic principle of the impedance mapping method and uses a single-phase diode rectifier circuit to demonstrate the modeling process. The resulting AC input impedance model is validated by detailed circuit simulation as well as experimental measurements","PeriodicalId":210889,"journal":{"name":"2006 IEEE Workshops on Computers in Power Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134171038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Steady State Electro-Thermal Modeling For DC-DC Converters DC-DC变换器稳态电热建模
2006 IEEE Workshops on Computers in Power Electronics Pub Date : 2006-07-16 DOI: 10.1109/COMPEL.2006.305628
R. Ciprian, B. Lehman
{"title":"Steady State Electro-Thermal Modeling For DC-DC Converters","authors":"R. Ciprian, B. Lehman","doi":"10.1109/COMPEL.2006.305628","DOIUrl":"https://doi.org/10.1109/COMPEL.2006.305628","url":null,"abstract":"This paper presents a method to combine CFD simulation with electrical simulation packages. This approach leads to highly accurate electro-thermal system modeling for DC-DC converters. Based on an initial power loss of main components and a thermal model of the converter, a user friendly CFD thermal simulation is used to obtain an initial point for case steady-state temperatures. These set of temperatures are then fed into temperature-dependent electrical models and simulations. The procedure can be repeated while error levels remain within an acceptable range. This approach can lead to a relatively accurate electro-thermal model at steady state","PeriodicalId":210889,"journal":{"name":"2006 IEEE Workshops on Computers in Power Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130972069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Digital Sliding Mode Pulsed Current Averaging IC Drivers for High Brightness Light Emitting Diodes 用于高亮度发光二极管的数字滑模脉冲电流平均IC驱动器
2006 IEEE Workshops on Computers in Power Electronics Pub Date : 2006-07-16 DOI: 10.1109/COMPEL.2006.305665
A. Bhattacharya, B. Lehman, A. Shteynberg, H. Rodriguez
{"title":"Digital Sliding Mode Pulsed Current Averaging IC Drivers for High Brightness Light Emitting Diodes","authors":"A. Bhattacharya, B. Lehman, A. Shteynberg, H. Rodriguez","doi":"10.1109/COMPEL.2006.305665","DOIUrl":"https://doi.org/10.1109/COMPEL.2006.305665","url":null,"abstract":"This paper proposes a digital controller with sliding mode pulsed current averaging scheme for high-brightness (HB) light emitting diodes (LED) IC drivers. The digital controller implements a control method to adjust the 'on time' of the active switch based on the comparison of output current and a reference current. The idea is to increase or decrease the duty cycle by discrete pulses in order to control the average current being delivered to the load. A variable frequency boost converter in discontinuous conduction mode (DCM) has been used to handle the required load current. No external analog-to-digital (A/D) converter is required for the application","PeriodicalId":210889,"journal":{"name":"2006 IEEE Workshops on Computers in Power Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125167389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Experimental High Performance Control of Two Permanent Magnet Synchronous Machines in an Integrated Drive for Automotive Applications 双永磁同步电机集成驱动的实验高性能控制
2006 IEEE Workshops on Computers in Power Electronics Pub Date : 2006-07-16 DOI: 10.1109/COMPEL.2006.305673
Lixin Tang, G. Su, Xianghui Huang
{"title":"Experimental High Performance Control of Two Permanent Magnet Synchronous Machines in an Integrated Drive for Automotive Applications","authors":"Lixin Tang, G. Su, Xianghui Huang","doi":"10.1109/COMPEL.2006.305673","DOIUrl":"https://doi.org/10.1109/COMPEL.2006.305673","url":null,"abstract":"Closed-loop control of an integrated dual-inverter which is able to drive two permanent magnet motors independently is presented and evaluated experimentally. By utilizing the neutral point of the main traction motor, only two inverter legs are needed for the two-phase auxiliary motor. A modified field oriented control scheme for this integrated inverter was introduced and employed in real-time control. Experimental results show that the inverter is able to control two drives independently. An integrated, component-count-reduced drive is achieved","PeriodicalId":210889,"journal":{"name":"2006 IEEE Workshops on Computers in Power Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122311984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
FPGA-Based Digital Network Analyzer for Digitally Controlled SMPS 基于fpga的数字网络分析仪用于数字控制SMPS
2006 IEEE Workshops on Computers in Power Electronics Pub Date : 2006-07-16 DOI: 10.1109/COMPEL.2006.305637
B. Miao, R. Zane, D. Maksimović
{"title":"FPGA-Based Digital Network Analyzer for Digitally Controlled SMPS","authors":"B. Miao, R. Zane, D. Maksimović","doi":"10.1109/COMPEL.2006.305637","DOIUrl":"https://doi.org/10.1109/COMPEL.2006.305637","url":null,"abstract":"This paper presents an FPGA-based digital network analyzer for digitally controlled switched-mode power supplies. Similar to standard network analyzers, the digital network analyzer can be used to validate converter models and the system design. The digital network analyzer can be built into the digital controller, resulting in an accurate measurement of the actual delays and non-idealities in the sampling and digital hardware. In addition, the approach requires relatively little additional hardware and/or software resources and reduces the costs in terms of equipment and engineering efforts. Experimental implementation on an FPGA and examples of 12 V-to-5 V 25 W buck converter open-loop and closed-loop frequency response measurements are shown","PeriodicalId":210889,"journal":{"name":"2006 IEEE Workshops on Computers in Power Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115271274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Feasibility of Geometric Digital Controls and Augmentation for Ultrafast Dc-Dc Converter Response 几何数字控制和超快Dc-Dc变换器响应增强的可行性
2006 IEEE Workshops on Computers in Power Electronics Pub Date : 2006-07-16 DOI: 10.1109/COMPEL.2006.305651
P. Krein
{"title":"Feasibility of Geometric Digital Controls and Augmentation for Ultrafast Dc-Dc Converter Response","authors":"P. Krein","doi":"10.1109/COMPEL.2006.305651","DOIUrl":"https://doi.org/10.1109/COMPEL.2006.305651","url":null,"abstract":"A set of augmentation-based controls is introduced for DC-DC converters. The controls support null response to disturbances in line or load for basic DC-DC converters. Augmentation resembles lossy snubbers, and takes the form of switched resistance to dissipate extra stored energy, resistive paths to deliver energy to the load while energy storage is increasing, and switched capacitance from an augmented phase to maintain the load during a transient. Cases are given for line step increases and decreases, and step load increases and decreases for buck and boost converters. It is shown that designs based on straightforward energy computations yield performance that remains within the specified output ripple band even during extreme transients","PeriodicalId":210889,"journal":{"name":"2006 IEEE Workshops on Computers in Power Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115385629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Hybrid DPWM with Digital Delay-Locked Loop 数字锁延环混合DPWM
2006 IEEE Workshops on Computers in Power Electronics Pub Date : 2006-07-16 DOI: 10.1109/COMPEL.2006.305666
V. Yousefzadeh, T. Takayama, D. Maksimović
{"title":"Hybrid DPWM with Digital Delay-Locked Loop","authors":"V. Yousefzadeh, T. Takayama, D. Maksimović","doi":"10.1109/COMPEL.2006.305666","DOIUrl":"https://doi.org/10.1109/COMPEL.2006.305666","url":null,"abstract":"This paper introduces a fully synthesizable hybrid digital pulse width modulator (DPWM). The DPWM includes a digital delay locked loop around a delay-line with discretely programmable delay cells to achieve constant-frequency clocked operation with the best possible resolution over a range of process or temperature variations. The DPWM module can implement trailing-edge, leading-edge or triangular modulation. It includes two outputs with programmable dead-times, suitable for DC-DC converters with synchronous rectifiers. The DPWM module is well suited for FPGA or custom chip implementation. Experimental results are shown for a 780 KHz, 10-bit FPGA realization","PeriodicalId":210889,"journal":{"name":"2006 IEEE Workshops on Computers in Power Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115565836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 123
Small signal modeling of hysteretic current mode control using the PWM switch model 利用PWM开关模型对滞后电流模式控制进行小信号建模
2006 IEEE Workshops on Computers in Power Electronics Pub Date : 2006-07-16 DOI: 10.1109/COMPEL.2006.305679
J.H. Park, B. Cho
{"title":"Small signal modeling of hysteretic current mode control using the PWM switch model","authors":"J.H. Park, B. Cho","doi":"10.1109/COMPEL.2006.305679","DOIUrl":"https://doi.org/10.1109/COMPEL.2006.305679","url":null,"abstract":"In this paper, based on the small signal analysis of switching power converters under a hysteretic current mode control, a unified PWM switch model is derived. The model is easy to handle because all manipulations are performed on a circuit diagram which includes simply-described function blocks indicating the physically intuitive relationships among the model parameters. This paper presents two kinds of small signal model of hysteretic current mode control such as critical current mode (CRM) variable frequency control and fixed-band current mode control methods. From the results of the PWM switch modeling, the dynamic characteristics of the hysteretic mode control scheme and that of the peak current mode (PCM) control are compared and summarized. Finally, both of the hysteretic current mode control models are verified by the experimental results","PeriodicalId":210889,"journal":{"name":"2006 IEEE Workshops on Computers in Power Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114659691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
A Universal Controller for Distributed Control of Power Electronics Conversion Systems 电力电子转换系统分布式控制的通用控制器
2006 IEEE Workshops on Computers in Power Electronics Pub Date : 2006-07-16 DOI: 10.1109/COMPEL.2006.305645
G. Francis, R. Burgos, F. Wang, D. Boroyevich
{"title":"A Universal Controller for Distributed Control of Power Electronics Conversion Systems","authors":"G. Francis, R. Burgos, F. Wang, D. Boroyevich","doi":"10.1109/COMPEL.2006.305645","DOIUrl":"https://doi.org/10.1109/COMPEL.2006.305645","url":null,"abstract":"This paper presents a distributed control system architecture for power electronics conversion systems. Control partitioning is described and a two-level control hierarchy is proposed. Specifically, a hardware manager-controlling the actual power conversion process-, and an application manager, hardware independent universal controller are introduced and implemented. A detailed description of these controllers is given using a voltage-source inverter as test system. Additionally, a high-speed real-time protocol (PESNet) is introduced for communication purposes of the proposed distributed control architecture. The synchronous nature of the protocol is described in addition to its data types and commands. From the analysis presented the usage of such an architecture and controllers for reconfigurable zonal distribution systems becomes apparent","PeriodicalId":210889,"journal":{"name":"2006 IEEE Workshops on Computers in Power Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121899233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Digitally controlled 10 MHz monolithic buck converter 数字控制的10mhz单片降压转换器
2006 IEEE Workshops on Computers in Power Electronics Pub Date : 2006-07-16 DOI: 10.1109/COMPEL.2006.305668
T. Takayama, D. Maksimović
{"title":"Digitally controlled 10 MHz monolithic buck converter","authors":"T. Takayama, D. Maksimović","doi":"10.1109/COMPEL.2006.305668","DOIUrl":"https://doi.org/10.1109/COMPEL.2006.305668","url":null,"abstract":"This paper describes design and implementation of a 10 MHz digitally controlled buck converter realized in a standard 0.35um CMOS process. Based on a discrete-time power-stage model, we show that a 3rd-order compensator can be designed for improved transient responses and disturbance rejection compared to standard 2nd-order PID compensators. Efficient hardware realization includes a look-up table type compensator, a 10-bit hybrid DPWM (2-bit counter, 5-bit delay-line, and 3-bit dither) and a power stage optimized for efficiency","PeriodicalId":210889,"journal":{"name":"2006 IEEE Workshops on Computers in Power Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123445357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
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