{"title":"A study of high density multilayer LSI","authors":"M. Matsunami, M. Koba, R. Miyake","doi":"10.1109/ICWSI.1990.63916","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63916","url":null,"abstract":"Describes a new type of high density multilayer LSI chip which is made up of several piled chips. Prescribed interconnections on the conventional wafer, are fabricated first. Thin chips with through-holes (about the size of pad) are fixed to the available parts of the under-layer chip. Each chip is interconnected through the holes. As a result, the chips will be equivalent to a hybrid IC which has several chips. This model is equal to the large scale high density LSI, the multichip substrate system, and hybrid WSI (Wafer Scale Integration).<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114265587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"WSI architecture for L-U decomposition: a radar array processor","authors":"V. Jain, D. Landis","doi":"10.1109/ICWSI.1990.63889","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63889","url":null,"abstract":"Presents a wafer scale architecture for a radar array processor. The computation intensive block in this processor is the L-U decomposition block, which is amenable to reconfigurable wafer implementation. The authors' design employs only two types of cells thus facilitating restructuring through laser linking and cutting. Details of these cells are presented as is the mapping of the algorithm to a systolic array architecture. In particular, the authors discuss the internal switches and multiplexers of the multiply-accumulate cell, and the external switches. Also described is the fast reciprocal cell which is expressly developed for this radar processor. Finally, the reconfiguration strategy is discussed.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115118890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}