Proceedings International Symposium on Quality Electronic Design最新文献_第7页

Mixed. PTL/static logic synthesis using genetic algorithms for low-power applications 好坏参半。PTL/静态逻辑合成使用遗传算法的低功耗应用

Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-03-18 DOI: 10.1109/ISQED.2002.996788

G. Cho, Tom Chen

引用次数: 6

Trends in low power digital system-on-chip designs 低功耗数字片上系统设计的趋势

Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-03-18 DOI: 10.1109/ISQED.2002.996775

R. Saleh, G. Lim, T. Kadowaki, K. Uchiyama

引用次数: 21

An EMI-noise analysis on LSI design with impedance estimation 基于阻抗估计的LSI设计emi噪声分析

Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-03-18 DOI: 10.1109/ISQED.2002.996724

K. Shimazaki, S. Hirano, H. Tsujikawa

引用次数: 4

Microwave III-V semiconductors for telecommunications and prospective of the III-V industry 电信用微波III-V半导体及III-V产业展望

Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-03-18 DOI: 10.1109/ISQED.2002.996734

Chan Wu

{"title":"Microwave III-V semiconductors for telecommunications and prospective of the III-V industry","authors":"Chan Wu","doi":"10.1109/ISQED.2002.996734","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996734","url":null,"abstract":"The microwave III-V semiconductor IC technology (primarily GaAs) has emerged as a powerful enabling technology for wireless and optical communications in the past 5 years. It has been dominating, or making substantial penetration into, the market for handset power amplifiers and switches, advanced wireless LAN RF front-ends and various other key RF components for broadband wireless, wireless infrastructure, satellite telecommunications, high data rate fiber optical communications and automotive radar applications. The microwave III-V semiconductor IC industry has grown dramatically in the past 2-3 years. It is worth noting that the majority of the recently formed GaAs fabs are located in Taiwan. Their intent is to provide pure-play foundry services following the silicon foundry business model developed by TSMC and UMC. In this presentation, we discuss the key components of III-V microwave transistors (HBT, pHEMT and MESFET etc.) and their RFICs/MMICs, their electrical performance, major applications, market status, trends and opportunities. We define the current status for the global III-V semiconductor industry, the rapidly growing GaAs MMIC fab industry in Taiwan and its advantages for providing a one-stop, total solution for wireless and optical communication components customers.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76562334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Using the Open Library Architecture (OLA) open source API in heterogeneous design flows 在异构设计流中使用开放库体系结构(OLA)开源API

Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-03-18 DOI: 10.1109/ISQED.2002.996696

Daniel Moritz

{"title":"Using the Open Library Architecture (OLA) open source API in heterogeneous design flows","authors":"Daniel Moritz","doi":"10.1109/ISQED.2002.996696","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996696","url":null,"abstract":"Design and timing closure are critical issues in modern design flows. Industry common library formats like .lib, CLF and TLF do not provide a means to embed arbitrary delay information and complex interconnect algorithms. Designers and silicon providers are at the mercy of these restrictions. Algorithms are applied to characterization data and proprietary interconnect analysis modules to minimize the error when mapping into these formats. The result is that numerous errors creep in to the tools that employ these formats. Often, these inaccuracies force unnecessary design iterations, technology guard banding, and finger pointing between the tool and library providers. With interconnect delay dominating path timing, it is more critical than ever to move past the text based library formats and to an API based solution that provides a way to embed interconnect analysis in the technology models. The Open Library Architecture addresses these issues by implementing an open C API. This API allows the library vendor to implement arbitrary data structures and algorithms. The same OLA module is employed consistently throughout the design flow which eliminates the loops which lead to inaccurate library mapping algorithms.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80539322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Productivity optimization techniques for the proactive semiconductor manufacturer 主动半导体制造商的生产率优化技术

Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-03-18 DOI: 10.1109/ISQED.2002.996727

D. Maynard

{"title":"Productivity optimization techniques for the proactive semiconductor manufacturer","authors":"D. Maynard","doi":"10.1109/ISQED.2002.996727","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996727","url":null,"abstract":"Summary form only given. The experienced semiconductor manufacturer is often confronted by apparently similar products that yield drastically different productivities. The same processes are used to fabricate these chips, yet the manufacturer's costs are clearly different. The customers expect similar pricing and a deviation must be accompanied by a credible explanation. Design for manufacturability (DFM) has become a popular industry term, yet many chip designers are uncertain where to start and what to implement. The semiconductor manufacturer possesses knowledge or suspicions of potential barriers and improvement opportunities. This information must be proactively fed forward to the design shops, which must also budget resources and time to address these items. This presentation describes how this process works, illustrated with examples from IBM Microelectronics' Vermont facility. Before focusing on productivity optimization, a recommended set of metrics is identified, and the concept of physical design characterization is overviewed. Past and existing designs provide excellent historical insight into a large number of issues that are often independent of technology node. While robust technology development objectives strive to minimize the potential manufacturing stumbling blocks, competitive pressures will balance these with other constraints. Ultimately, it is decisions made by a designer that will determine the level of productivity achievable. Much of this presentation is devoted to describing a number of these decisions. In addition, the manufacturer may deploy complex algorithms to adjust the design to process constraints. Another, but more costly solution is for the manufacturer to tailor the process to a specific product, compensating for identified product-technology gaps. Lastly, this presentation ties these concepts together into a recommended business process.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81144936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process 亚四分之一微米CMOS工艺中衬底触发技术的混合电压I/O电路ESD保护设计

Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-03-18 DOI: 10.1109/ISQED.2002.996768

M. Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo

引用次数: 10

Advancing quality of EDA software 提高EDA软件质量

Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-03-18 DOI: 10.1109/ISQED.2002.996699

G. Ben-Yaacov, P. Suratkar, M. Holliday, K. Bartleson

引用次数: 5

Organization of a microprocessor design process using Internet-based interoperable workflows 使用基于internet的可互操作工作流组织微处理器设计过程

Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-03-18 DOI: 10.1109/ISQED.2002.996780

N. Q. Trung, A. Kokoszka, K. Siekierska, A. Pawlak, D. Obrebski, Norbert Lugowski

引用次数: 2

Modeling and design of a low-voltage SOI suspended-gate MOSFET (SG-MOSFET) with a metal-over-gate architecture 金属过闸结构的低压SOI悬栅MOSFET (SG-MOSFET)的建模与设计

Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-03-18 DOI: 10.1109/ISQED.2002.996794

A. Ionescu, V. Pott, R. Fritschi, K. Banerjee, M. Declercq, P. Renaud, C. Hibert, P. Fluckiger, G. Racine

引用次数: 81