亚四分之一微米CMOS工艺中衬底触发技术的混合电压I/O电路ESD保护设计

M. Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo
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引用次数: 10

摘要

为了提高混合电压I/O电路中堆叠nmos器件的ESD保护效率,提出了一种衬底触发技术。衬底触发技术可以进一步降低堆叠nmos器件的触发电压,确保混合电压I/O电路的有效ESD保护。采用衬底触发技术制备了用于2.5 V/3.3 V容限混合电压I/O电路的ESD保护电路,并在0.25-/spl mu/m盐化CMOS工艺中进行了验证。实验结果表明,通过衬底触发设计,混合电压I/O电路的HBM ESD稳健性可提高65%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process
A substrate-triggered technique is proposed to improve ESD protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique, can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the substrate-triggered technique for 2.5 V/3.3 V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-/spl mu/m salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased /spl sim/65% by this substrate-triggered design.
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