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Proceedings International Symposium on Quality Electronic Design最新文献

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Improving the efficiency and quality of simulation-based behavioral model verification using dynamic Bayesian criteria 利用动态贝叶斯准则提高基于仿真的行为模型验证的效率和质量
Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-08-07 DOI: 10.1109/ISQED.2002.996761
A. Hajjar, Tom Chen
{"title":"Improving the efficiency and quality of simulation-based behavioral model verification using dynamic Bayesian criteria","authors":"A. Hajjar, Tom Chen","doi":"10.1109/ISQED.2002.996761","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996761","url":null,"abstract":"In order to improve the effectiveness of simulation-based behavioral verification, it is important to determine when to stop the current test strategy and to switch to an expectantly more rewarding test strategy. The location of a stopping point is dependent on the statistical model one chooses to describe the coverage behavior during verification. In this paper, we present dynamic Bayesian (DB) and confidence-based dynamic Bayesian (CDB) stopping rules for behavioral VHDL model verification. The statistical assumptions of the proposed stopping rules are based on experimental evaluation of probability distribution functions and correlation functions. Fourteen behavioral VHDL models were experimented with to determine the high efficiency of the proposed stopping rules over the existing ones. Results show that the DB and the CDB stopping rules outperform all the existing stopping rules with an average improvement of at least 69% in coverage per testing patterns used.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"51 1","pages":"304-309"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87567786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Future SoC design challenges and solutions 未来SoC设计挑战与解决方案
Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-08-07 DOI: 10.1109/ISQED.2002.996800
C. C. Chen, Ed Cheng
{"title":"Future SoC design challenges and solutions","authors":"C. C. Chen, Ed Cheng","doi":"10.1109/ISQED.2002.996800","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996800","url":null,"abstract":"SoC (system on a chip) design creates tremendous design challenges to the traditional VLSI ASIC design. It covers not only the traditional DSM (deep sub-micron) issues but also the integration issues such as IP and signal integrity especially for integrated digital/analog system such as Bluetooth. Besides. power consumption and power delivery also impose huge design constraints to the already difficult situation especially for the portable and mobile devices. This talk will introduce and analysis the potential SoC issues and potential solutions from the architecture level to the circuit level.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"22 1","pages":"534-537"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81000570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
On the relation between SAT and BDDs for equivalence checking 等效检验中SAT与bdd的关系
Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-08-07 DOI: 10.1109/ISQED.2002.996778
S. Reda, R. Drechsler, A. Orailoglu
{"title":"On the relation between SAT and BDDs for equivalence checking","authors":"S. Reda, R. Drechsler, A. Orailoglu","doi":"10.1109/ISQED.2002.996778","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996778","url":null,"abstract":"State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on binary decision diagrams (BDDs) and SAT (Boolean satisfiability) solvers. In this paper, we study the relation between the two procedures and show how the number of backtracks obtained in the Davis-Putnam (DP) procedure is linked to the number of paths in the BDD. We utilize this relation to devise a method that uses BDD variable ordering techniques to run the DP procedure. Experimental results confirm that the proposed method results in a dramatic decrease in the number of backtracks and in the time needed to prove the Boolean satisfiability problem as well.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"40 1","pages":"394-399"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76189605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
On dynamic delay and repeater insertion in distributed capacitively coupled interconnects 分布式电容耦合互连中的动态延迟和中继器插入
Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-08-07 DOI: 10.1109/ISQED.2002.996740
D. Pamunuwa, H. Tenhunen
{"title":"On dynamic delay and repeater insertion in distributed capacitively coupled interconnects","authors":"D. Pamunuwa, H. Tenhunen","doi":"10.1109/ISQED.2002.996740","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996740","url":null,"abstract":"Repeater insertion is a well established technique to minimise the propagation delay over long resistive interconnects. In deep sub-micron technologies, as the wires are spaced ever closer and signal rise and fall times go into the sub-nanosecond region, increased crosstalk has implications for the data throughput and signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. We show that in uniform coupled lines, the response for several important switching patterns has a dominant pole characteristic. The effect of repeater insertion including optimal repeater insertion for minimising delay with worst-case cross-talk, and area constrained optimisation is considered. All equations are checked against a dynamic circuit simulator (SPECTRE).","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"20 1","pages":"240-245"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88588742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Studying the impact of gate tunneling on dynamic behaviors of partially-depleted SOI CMOS using BSIMPD 利用BSIMPD研究栅极隧道效应对部分耗尽SOI CMOS动态特性的影响
Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-08-07 DOI: 10.1109/ISQED.2002.996792
P. Su, S. Fung, Weidong Liu, C. Hu
{"title":"Studying the impact of gate tunneling on dynamic behaviors of partially-depleted SOI CMOS using BSIMPD","authors":"P. Su, S. Fung, Weidong Liu, C. Hu","doi":"10.1109/ISQED.2002.996792","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996792","url":null,"abstract":"In this, work, we investigate and analyze the impact of gate tunneling on dynamic behaviors of partially depleted SOI CMOS with the aid of the physically accurate BSIMPD model. We examine in particular the impact of gate tunneling on the history dependence of inverter delays. The examination reveals key requirements for capturing the history effect in SPICE modeling. This study suggests that gate tunneling has a strong impact on the delay range and should be considered in SOI circuit simulation. It is crucial for circuit, designers to understand and contain the hysteretic delay variations caused by gate current. An accurate SPICE model that includes the oxide tunneling mechanism should be used to quantify the effect without undermining the performance benefit of a partially depleted SOI technology. BSIMPD is one model that attempts to bridge the gap between advanced SOI technologies and circuit design. With its built-in floating-body, self-heating and body-contact modules, BSIMPD captures SOI-specific effects and therefore is able to raise the design quality of PD SOI chips. BSIMPD has been implemented in Berkeley SPICE3f4 and other commercial SPICE simulators. It may also be the basis for computing the look-up tables used for higher-level timing simulation.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"956 1","pages":"487-491"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85616100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Economic analysis of a stopping-rule in branch coverage testing 分支覆盖测试中停止规则的经济分析
Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-08-07 DOI: 10.1109/ISQED.2002.996770
M. Sahinoglu, Scott Glover
{"title":"Economic analysis of a stopping-rule in branch coverage testing","authors":"M. Sahinoglu, Scott Glover","doi":"10.1109/ISQED.2002.996770","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996770","url":null,"abstract":"This paper argues that software testing can be less thorough yet more cost-efficient if applied in a well-managed, empirical manner across the entire Software Development Life Cycle (SDLC). This is done by showing the cost-benefit analyses among other criteria. To ensure success, testing must be planned and executed within an Earned Value Management (EVM) paradigm as the experiment is conducted on a statistical-process controlled mindset. The Stopping Rule (MESAT) is applied to an actual embedded-chip software development cycle to show potential gains compared to archaic testing methods or none that were used. The result is that a considerable percentage of the particular testing effort could have been saved under usual circumstances, had the testing been planned and executed under EVM with the MESAT algorithm.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"47 1","pages":"341-346"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84760268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Trading off reliability and power-consumption in ultra-low power systems 在超低功耗系统中权衡可靠性和功耗
Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-08-07 DOI: 10.1109/ISQED.2002.996773
A. Maheshwari, W. Burleson, R. Tessier
{"title":"Trading off reliability and power-consumption in ultra-low power systems","authors":"A. Maheshwari, W. Burleson, R. Tessier","doi":"10.1109/ISQED.2002.996773","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996773","url":null,"abstract":"Critical systems like pace-makers, defibrillators, wearable computers and other electronic gadgets have to be designed not only for reliability but also for ultra-low power consumption due to limited battery life. This paper explores architecture, logic and circuit level approaches to this tradeoff. Fault tolerance techniques at the architecture level can be broadly classified into spatial or temporal redundancy. Using an example of counters (binary and Gray) we show that temporal redundancy is best suited for these ultra-low power and low performance systems as it consumes 30% less power than an area redundant technique. Circuit techniques allow power-reliability tradeoffs of about 50% in each measure. A methodology is developed based on low-level fault simulation using SPICE, which allows detailed circuit models for both power consumption and reliability in current and future CMOS technology.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"77 1","pages":"361-366"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73025762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
AC analysis of thin gate oxide MOS with quantum mechanical corrections 基于量子力学修正的薄栅氧化物MOS交流分析
Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-08-07 DOI: 10.1109/ISQED.2002.996767
T. Oh, Zhiping Yu, R. Dutton
{"title":"AC analysis of thin gate oxide MOS with quantum mechanical corrections","authors":"T. Oh, Zhiping Yu, R. Dutton","doi":"10.1109/ISQED.2002.996767","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996767","url":null,"abstract":"MOS device scaling into the deep submicron regime inevitably relies on thinner gate oxide and higher substrate doping. Quantum mechanical effects must be considered in device design. This paper presents a density-gradient model which expresses the quantum mechanical effects using macroscopic approximation, and AC analysis based on it. 1D and 2D computer simulations of AC analysis show QM effects on threshold voltage and current with different gate oxide thickness and substrate doping. A simple technique to extract device parameters for circuit design is also presented.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"41 1","pages":"326-330"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79634769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design method and automation of comparator generation for flash A/D converter flash A/D转换器比较器生成的设计方法及自动化
Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-08-07 DOI: 10.1109/ISQED.2002.996716
Daegyu Lee, Jincheol Yoo, Kyusun Choi
{"title":"Design method and automation of comparator generation for flash A/D converter","authors":"Daegyu Lee, Jincheol Yoo, Kyusun Choi","doi":"10.1109/ISQED.2002.996716","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996716","url":null,"abstract":"The design methods and the automation of the comparator circuit layout generation for a flash A/D converter are presented in this paper. The threshold inverter quantization (TIQ) based A/D converters require 2/sup n/ - 1 comparators, each one different from all others. Optimal design method of the TIQ comparator presented in this paper significantly improves the linearity of the A/D converter against the CMOS process variation. Especially the DNL dependence on the CMOS process variation can be almost eliminated. The design method has been incorporated into a software package and the 2/sup n/ - 1 optimized TIQ comparator layouts are generated as an output of the software package. The simulation results are presented to show the effectiveness of the design methods. Also, the prototype chip has been fabricated, with initial test results confirming the DNL reduction.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"21 1","pages":"138-142"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78674459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
Promising directions in hardware design verification 硬件设计验证的发展方向
Proceedings International Symposium on Quality Electronic Design Pub Date : 2002-08-07 DOI: 10.1109/ISQED.2002.996776
S. Qadeer, S. Tasiran
{"title":"Promising directions in hardware design verification","authors":"S. Qadeer, S. Tasiran","doi":"10.1109/ISQED.2002.996776","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996776","url":null,"abstract":"Ensuring the functional correctness of hardware early in the design cycle is crucial for both economic and methodological reasons. However, current verification techniques are inadequate for industrial designs. Formal verification techniques are exhaustive but do not scale; partial verification techniques based on simulation scale well but are not exhaustive. This paper discusses promising approaches for improving the scalability of formal verification and comprehensiveness of partial verification.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"108 1","pages":"381-387"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84980401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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