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2008 Forum on Specification, Verification and Design Languages最新文献

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TLM-based verification of a combined switching Networks-on-Chip router 基于tlm的组合交换片上网络路由器验证
2008 Forum on Specification, Verification and Design Languages Pub Date : 2008-10-10 DOI: 10.1109/FDL.2008.4641462
M. Sabry, M. El-Kharashi, H.S. Bedor, A. Salem
{"title":"TLM-based verification of a combined switching Networks-on-Chip router","authors":"M. Sabry, M. El-Kharashi, H.S. Bedor, A. Salem","doi":"10.1109/FDL.2008.4641462","DOIUrl":"https://doi.org/10.1109/FDL.2008.4641462","url":null,"abstract":"TLM-based verification is proposed to verify an RTL implementation of a networks-on-chip router that is capable of doing a combined circuit and packet switching. The router architecture is developed in both RTL and TLM. A transactor was modeled to embed the RTL implementation of the router into same TLM simulation environment and used to verify the functionality of the RTL model. Results show that the functionality of both RTL and TLM models are identical.","PeriodicalId":202172,"journal":{"name":"2008 Forum on Specification, Verification and Design Languages","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115741904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Model-based Design Space Exploration for RTES with SysML and MARTE 基于SysML和MARTE的RTES模型设计空间探索
2008 Forum on Specification, Verification and Design Languages Pub Date : 2008-10-10 DOI: 10.1109/FDL.2008.4641446
M. Mura, L. Murillo, M. Prevostini
{"title":"Model-based Design Space Exploration for RTES with SysML and MARTE","authors":"M. Mura, L. Murillo, M. Prevostini","doi":"10.1109/FDL.2008.4641446","DOIUrl":"https://doi.org/10.1109/FDL.2008.4641446","url":null,"abstract":"The features of the emerging modeling languages for system design allow designers to build models of almost any kind of heterogeneous hardware-software systems, including real time embedded systems (RTES). An important goal to achieve is the implementation and use of these models in all the steps of a common design flow. One of these steps is the design space exploration (DSE), which helps designers in discovering the optimal solutions among all possible combinations after mapping functional to architectural specifications; for RTES this step is particularly hard as it should include scheduling analysis in order to proof the time validity after the mapping. This paper presents some guidelines on how to use SysML and MARTE profiles to identify design points fulfilling the timing constraints of an RTES, and thus allowing to automate DSE analysis within the system design phase.","PeriodicalId":202172,"journal":{"name":"2008 Forum on Specification, Verification and Design Languages","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123761483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
The performance of combining multiway decision graphs and HOL theorem prover 多路决策图与HOL定理相结合的性能证明
2008 Forum on Specification, Verification and Design Languages Pub Date : 2008-10-10 DOI: 10.1109/FDL.2008.4641435
Sa'ed Abed, O. Mohamed, G. A. Sammane
{"title":"The performance of combining multiway decision graphs and HOL theorem prover","authors":"Sa'ed Abed, O. Mohamed, G. A. Sammane","doi":"10.1109/FDL.2008.4641435","DOIUrl":"https://doi.org/10.1109/FDL.2008.4641435","url":null,"abstract":"In this paper, we are interested in defining a platform for high level model checking using multiway decision graphs (MDGs) within high order logic. The platform is based on the logical formulation of an MDG as a directed formulae (DF). The DF is defined in the HOL theorem prover where the many sorted first-order logic is characterized as a HOL built-in data type. Then, the HOL inference rules are defined to check the well-formedness conditions of any directed formula. Based on this formalization, the MDGs operations are defined as inference rules and consistency and well-formedness proof of each operation is provided. Finally, some experimental results are presented to show the performance of the MDG-HOL platform. The obtained results show that this platform offers a considerable gain in terms of automation without sacrificing CPU time and memory usage.","PeriodicalId":202172,"journal":{"name":"2008 Forum on Specification, Verification and Design Languages","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114909910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Using SystemC for an extended MATLAB/Simulink verification flow 使用SystemC进行扩展的MATLAB/Simulink验证流程
2008 Forum on Specification, Verification and Design Languages Pub Date : 2008-10-10 DOI: 10.1109/FDL.2008.4641449
Kai Hylla, Jan-Hendrik Oetjens, W. Nebel
{"title":"Using SystemC for an extended MATLAB/Simulink verification flow","authors":"Kai Hylla, Jan-Hendrik Oetjens, W. Nebel","doi":"10.1109/FDL.2008.4641449","DOIUrl":"https://doi.org/10.1109/FDL.2008.4641449","url":null,"abstract":"Functional verification is a major part of todaypsilas system design task. Several approaches are available for verification on a high abstraction level, where designs are often modeled using MATLAB/Simulink, as well as for RT-level verification. Different approaches are a barrier to a unified verification flow. For simulation based RT-level verification, an extended test bench concept has been developed at Robert Bosch GmbH. This paper describes how this SystemC-based concept can be applied to Simulink models. The implementation of the resulting verification flow addresses the required synchronization of both simulation environments, as well as data type conversion. An example is used to evaluate the implementation and the whole verification flow. It is shown that using the extended verification flow saves a significant amount of time during development. Reusing test bench modules and test cases preserves consistency of the test bench. Verification is done automatically rather than by inspecting the waveform manually. The extended verification flow unifies system-level and RT-level verification, yielding a holistic verification flow.","PeriodicalId":202172,"journal":{"name":"2008 Forum on Specification, Verification and Design Languages","volume":"293 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116872958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Comparison of ASCET and UML - Preparations for an abstract software architecture ASCET和UML的比较——抽象软件体系结构的准备
2008 Forum on Specification, Verification and Design Languages Pub Date : 2008-10-10 DOI: 10.1109/FDL.2008.4641451
Dirk Ahrens, A. Pfeiffer, T. Bertram
{"title":"Comparison of ASCET and UML - Preparations for an abstract software architecture","authors":"Dirk Ahrens, A. Pfeiffer, T. Bertram","doi":"10.1109/FDL.2008.4641451","DOIUrl":"https://doi.org/10.1109/FDL.2008.4641451","url":null,"abstract":"For efficient software engineering in automotive applications the executed design processes must separate general properties and characteristics of the created system from implementation and realisation details as long as possible. This short paper shows how software architectures can be displayed on an abstract level by using the Unified Modeling Language (UML) and how these abstract depictions can be transferred to commonly used design and code generation tools either manually or by automation. Formal methods and transformation rules can be applied by using the Extensible Markup Language (XML). The methods are exemplarily shown for ASCET SE by ETAS.","PeriodicalId":202172,"journal":{"name":"2008 Forum on Specification, Verification and Design Languages","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127892538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Refining power consumption estimations in the component based AADL design flow 在基于AADL设计流程的组件中改进功耗估计
2008 Forum on Specification, Verification and Design Languages Pub Date : 2008-10-10 DOI: 10.1109/FDL.2008.4641441
E. Senn, J. Laurent, E. Juin, J. Diguet
{"title":"Refining power consumption estimations in the component based AADL design flow","authors":"E. Senn, J. Laurent, E. Juin, J. Diguet","doi":"10.1109/FDL.2008.4641441","DOIUrl":"https://doi.org/10.1109/FDL.2008.4641441","url":null,"abstract":"This paper presents a method that permits to quickly estimate the power consumption at the first steps of a systempsilas design. We present multi-level power models and show how to use them at different levels of the specification refinement in the component based AADL design flow. PET, a power estimation tool, is being developed in the frame of the European SPICES project. It first prototype gives, in the case of a processor binding, power consumption estimations, for software components in the AADL component assembly model, with a maximal error ranging roughly from 5% to 30% depending on the refinement level. We illustrate our approach with the power model of the PowerPC 405, and its use at different levels in the AADL flow.","PeriodicalId":202172,"journal":{"name":"2008 Forum on Specification, Verification and Design Languages","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133634448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A model driven development approach for implementing reactive systems in hardware 用于在硬件中实现响应式系统的模型驱动开发方法
2008 Forum on Specification, Verification and Design Languages Pub Date : 2008-10-10 DOI: 10.1109/FDL.2008.4641445
Zhonglei Wang, A. Herkersdorf, Stefano Merenda, Michael Tautschnig
{"title":"A model driven development approach for implementing reactive systems in hardware","authors":"Zhonglei Wang, A. Herkersdorf, Stefano Merenda, Michael Tautschnig","doi":"10.1109/FDL.2008.4641445","DOIUrl":"https://doi.org/10.1109/FDL.2008.4641445","url":null,"abstract":"To deal with the increasing complexity of digital systems, the model driven development approach has proven to be beneficial. This paper presents a model driven hardware design process that is dedicated to reactive embedded systems. The approach is based on the component language (COLA), a synchronous data flow language with formal semantics. COLA follows the hypothesis of perfect synchrony. Models thus do not assume specific timing properties and remain deterministic as long as data flow requirements are retained. This is an essential feature for modeling safety-critical systems. Further, the well-defined semantics not only allows that the resulting models can be formally reasoned about, but is also the key to translation to domain-specific languages. This paper describes the approach of translating the models to VHDL descriptions from their graphical representations. As COLA is well-adapted to both data flow description and control automata, the generated VHDL code can be synthesized to very efficient FPGA circuits, comparable to that synthesized from hand-written VHDL code according to our case study.","PeriodicalId":202172,"journal":{"name":"2008 Forum on Specification, Verification and Design Languages","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133207050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Towards a common HW/SW interface-centric and component-oriented specification and design methodology 朝向一个通用的以硬件/软件接口为中心和面向组件的规范和设计方法
2008 Forum on Specification, Verification and Design Languages Pub Date : 2008-10-10 DOI: 10.1109/FDL.2008.4641417
G. Gailliard, Hugues Balp, C. Jouvray, F. Verdier
{"title":"Towards a common HW/SW interface-centric and component-oriented specification and design methodology","authors":"G. Gailliard, Hugues Balp, C. Jouvray, F. Verdier","doi":"10.1109/FDL.2008.4641417","DOIUrl":"https://doi.org/10.1109/FDL.2008.4641417","url":null,"abstract":"In the scope of initial discussions about a standard OMG IDL-to-VHDL language mapping, we present some requirements and propose a configurable mapping. We demonstrate the advantages of a common component-oriented approach to specify HW and SW interfaces compared to previous object-oriented approaches. Our proposition is based on a family of hardware interfaces enabling to represent various interaction semantics and mapping configurations. Our approach is illustrated through the CORBA component model (CCM).","PeriodicalId":202172,"journal":{"name":"2008 Forum on Specification, Verification and Design Languages","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131409855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Generating MARTE allocation models from activity threads 从活动线程生成MARTE分配模型
2008 Forum on Specification, Verification and Design Languages Pub Date : 2008-10-10 DOI: 10.1109/FDL.2008.4641448
A. Liehr, Heike S. Rolfs, K. Buchenrieder, U. Nageldinger
{"title":"Generating MARTE allocation models from activity threads","authors":"A. Liehr, Heike S. Rolfs, K. Buchenrieder, U. Nageldinger","doi":"10.1109/FDL.2008.4641448","DOIUrl":"https://doi.org/10.1109/FDL.2008.4641448","url":null,"abstract":"UML and specialized profiles, such as MARTE, are established specification and modeling procedures in the system development process. While language-based system specification and resource modeling shortens the design cycle, the exploration of the design-space is time-consuming. Most expensive proves the generation of system models respectively the architectural alternatives for exploration. This work contributes a method that utilizes activity threads to reduce the effort, needed to build such a set. With this method, a group of system models, each representing one design alternative, can automatically be generated. Therefore, only one architecture model and one function model in combination with an activity thread is required. The proposed method is the first step towards automated comparison of the performance for design alternatives at an early stage in the development process.","PeriodicalId":202172,"journal":{"name":"2008 Forum on Specification, Verification and Design Languages","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133739367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Towards compilation of streaming programs into FPGA hardware 面向FPGA硬件的流程序编译
2008 Forum on Specification, Verification and Design Languages Pub Date : 2008-10-10 DOI: 10.1109/FDL.2008.4641423
F. Plavec, Z. Vranesic, S. Brown
{"title":"Towards compilation of streaming programs into FPGA hardware","authors":"F. Plavec, Z. Vranesic, S. Brown","doi":"10.1109/FDL.2008.4641423","DOIUrl":"https://doi.org/10.1109/FDL.2008.4641423","url":null,"abstract":"There is an increasing need for automated conversion of high-level design descriptions into hardware. We present a flow that converts a software application written in the Brook streaming language into a hardware description targeting FPGAs. We use a combination of our source-to-source compiler and a commercial C2H behavioral synthesis compiler. Our approach results in a significant through-put increase compared to software and ordinary C2H results (up to 8.9X and 4.3X, respectively). The throughput can be further increased by using more hardware resources to exploit data parallelism available in streaming applications.","PeriodicalId":202172,"journal":{"name":"2008 Forum on Specification, Verification and Design Languages","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129826418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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