TLM-based verification of a combined switching Networks-on-Chip router

Abstract

TLM-based verification is proposed to verify an RTL implementation of a networks-on-chip router that is capable of doing a combined circuit and packet switching. The router architecture is developed in both RTL and TLM. A transactor was modeled to embed the RTL implementation of the router into same TLM simulation environment and used to verify the functionality of the RTL model. Results show that the functionality of both RTL and TLM models are identical.