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DoE simulations and measurements with the microDAC stress chip for material and package investigations 使用microDAC应力芯片进行DoE模拟和测量，用于材料和封装研究

18th European Microelectronics & Packaging Conference Pub Date : 2010-11-22 DOI: 10.1109/ESTC.2010.5642977

F. Schindler-Saefkow, A. Otto, S. Rzepka, O. Wittler, B. Wunderle, B. Michel

{"title":"DoE simulations and measurements with the microDAC stress chip for material and package investigations","authors":"F. Schindler-Saefkow, A. Otto, S. Rzepka, O. Wittler, B. Wunderle, B. Michel","doi":"10.1109/ESTC.2010.5642977","DOIUrl":"https://doi.org/10.1109/ESTC.2010.5642977","url":null,"abstract":"The in-situ detection of failures in microelectronic packages in an experiment is still a big challenge. The reliability of most packages will be qualified by measuring the electrical resistance of daisy chain structures. The moment of failure in the electrical sig-nals or the changes in the resistance are used for reliability or lifetime estimations. But the correlation of electrical resistance in the metallization and the packages or system reliability is very low. Extremely time-consuming investigation is needed to localize package failure after the experiment.Therefore, a chip, the MicroDAC stress chip, has been developed in a publicly funded project that is able to measure stress induced by thermo-mechanical loads. Different components of the stress tensor can be read out, as e.g. the in-plane stress difference and the in-plane shear stress on the chip surface within a 300 µm grid. This enables in-situ determination of the stress state even when the die is packaged and molded over. Residual stresses induced by processing steps as well as degradation within the materi-als or interfaces can thus be detected and measured. /1; 2/. A further advantage is the simple read out procedure which needs only four wire bond or flip-chip bump connec-tions. With this chip it is possible to get answers about what happened with the package during the temperature cycling tests. How fast is the failure growing from one cycle to the next and when is the failure mechanism changing in the experiment? What is the influence of vibration or moisture on the stress?","PeriodicalId":199477,"journal":{"name":"18th European Microelectronics & Packaging Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129842424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Chip embedding technology developments leading to the emergence of miniaturized system-in-packages 芯片嵌入技术的发展导致了小型化系统级封装的出现

18th European Microelectronics & Packaging Conference Pub Date : 2010-06-01 DOI: 10.1109/ECTC.2010.5490733

D. Manessis, L. Boettcher, S. Karaszkiewicz, A. Ostmann, R. Aschenbrenner, K. Lang

{"title":"Chip embedding technology developments leading to the emergence of miniaturized system-in-packages","authors":"D. Manessis, L. Boettcher, S. Karaszkiewicz, A. Ostmann, R. Aschenbrenner, K. Lang","doi":"10.1109/ECTC.2010.5490733","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490733","url":null,"abstract":"At PCB manufacturing level, 50 µm thin chips have been embedded with pitches up to 200 µm in up to 18″×24″ panels using face-down technology for chip assembly. This paper describes in detail the merits and shortcomings of both face-down and face-up embedding. In addition, it shows the further developments in chip embedding technologies to incorporate chips with even smaller pitches up to 50µm. Embedding of small pitch chips has been realised with concurrent developments in accurate chip positioning, plating methods and chemistries and ultra fine line patterning. The results in this paper show the emergence of a new prototype Embedded chip-QFN package with contact pads at 400µm pitch and a total number of 84I/Os with dimensions of 10mm×10mm. The embedded chip in the QFN package is 5mm×5mm in size and has a peripheral pad configuration at 100µm pitch. All Embedded chip-QFN packages have been manufactured in 10″×14″ panels at prototype level. This paper also shows the latest developments in semi-additive processes for copper structuring of chip embedded packages with pitches lower than 100µm. Ultra fine line structuring technology has been developed up to 15µm L/S copper structures using innovative 2µm copper base foils. Qualitative analysis using acoustic microscopy and shear testing of the QFNs provides evidence of good resin adhesion and package mechanical robustness. Furthermore, this study shows promising results for embedding of chips with pitches dwon to 50µm, introducing a new “vialess” face-down embedding approach where direct contacts are established between copper pads and functional copper foil. Developmental work on “vialess” embedding technology is still ongoing.","PeriodicalId":199477,"journal":{"name":"18th European Microelectronics & Packaging Conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115950900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20