DoE simulations and measurements with the microDAC stress chip for material and package investigations

Abstract

The in-situ detection of failures in microelectronic packages in an experiment is still a big challenge. The reliability of most packages will be qualified by measuring the electrical resistance of daisy chain structures. The moment of failure in the electrical sig-nals or the changes in the resistance are used for reliability or lifetime estimations. But the correlation of electrical resistance in the metallization and the packages or system reliability is very low. Extremely time-consuming investigation is needed to localize package failure after the experiment.Therefore, a chip, the MicroDAC stress chip, has been developed in a publicly funded project that is able to measure stress induced by thermo-mechanical loads. Different components of the stress tensor can be read out, as e.g. the in-plane stress difference and the in-plane shear stress on the chip surface within a 300 µm grid. This enables in-situ determination of the stress state even when the die is packaged and molded over. Residual stresses induced by processing steps as well as degradation within the materi-als or interfaces can thus be detected and measured. /1; 2/. A further advantage is the simple read out procedure which needs only four wire bond or flip-chip bump connec-tions. With this chip it is possible to get answers about what happened with the package during the temperature cycling tests. How fast is the failure growing from one cycle to the next and when is the failure mechanism changing in the experiment? What is the influence of vibration or moisture on the stress?