2012 IEEE International Symposium on Electromagnetic Compatibility最新文献_第3页

On-chip design techniques for reducing power supply noise effects on ADC with chip-PCB hierarchical structure 芯片- pcb层次化结构降低ADC电源噪声影响的片上设计技术

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351672

Bumhee Bae, Jonghyun Cho, Joungho Kim

{"title":"On-chip design techniques for reducing power supply noise effects on ADC with chip-PCB hierarchical structure","authors":"Bumhee Bae, Jonghyun Cho, Joungho Kim","doi":"10.1109/ISEMC.2012.6351672","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351672","url":null,"abstract":"In this paper, we propose the on-chip design techniques for controlling Power Supply Noise (PSN) effects on Analog-to-Digital Converter (ADC) with chip-Printed Circuit Board (PCB) hierarchical structure interconnected by bonding wires. There are two steps for explaining the proposed design technique. First, we explain what the PSN coupling path is on ADC. The PSN will couple from noise source to noise victim via power distribution network and circuit path. Second, we propose how we can reduce the noise coupling effects. The comparator is essential circuit to ADC and most sensitive circuit to PSN in ADC. Therefore, it is important to reduce the noise coupling effects on comparator for designing ADC which is non-sensitive to PSN. The comparator has two input nodes, and the differential voltage between two input nodes affect to ADC output. The impedance imbalance between two comparator inputs is the reason why the comparator is sensitive to PSN. So, the technique which is for balancing two input impedance is important to reduce PSN effects. We consider chip-PCB components to estimate two input impedance, because the two input impedances are affected by chip-PCB hierarchical structure. If we control the impedance of each input, we can design the ADC which is nonsensitive to PSN at the targeted frequency. We demonstrate the proposed technique based on simulation by PSN whose frequency swept from 1MHz to 3GHz.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134644979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The Generalized ICN for 25Gbps+ channel using NRZ, PAM-M or Duobinary coding scheme 25Gbps+信道通用ICN采用NRZ、PAM-M或双二进制编码方案

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351756

Cong Gao, Ji Chen, Xin Wu, P. Amleshi

引用次数: 7

Near-field coupling method for a complex navy ship environment 舰船复杂环境下的近场耦合方法

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351774

P. Deschenes, M. Coulombe, R. Paknys, A. Pinchuk

引用次数: 5

Improved wavelet-based techniques for power quality evaluation in three-phase systems 改进的基于小波的三相系统电能质量评估技术

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351668

I. Nicolae, P. Nicolae, M. Nicolae

{"title":"Improved wavelet-based techniques for power quality evaluation in three-phase systems","authors":"I. Nicolae, P. Nicolae, M. Nicolae","doi":"10.1109/ISEMC.2012.6351668","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351668","url":null,"abstract":"The paper deals with the analysis based on the Discrete Wavelet Transform (DWT) of stationary regimes in three-phase power systems with significant distortions. Firstly one presents the conclusion of preliminary evaluations used to select the most appropriate analysis technique: RMS values were evaluated using different DWT-based methods, analysis of errors, of memory consumptions and respectively of runtimes was done. Afterward data gathered from the excitation of the main generator from a power plant were submitted to a complex analysis. Three DWT-based methods were selected for comparative studies: one relies on the function dwt, provided by Matlab, the other two rely on original functions implementing the so-called “D4 Wavelet Transform” (“dwm” assumes that the analysed signal is periodic, whilst “dwi” performs interpolations, being applicable to non-periodic signals as well). The superiority of dwm and dwi is sustained by smaller errors (results yielded by the Fast Fourier Transform (FFT) were used as reference) and significantly smaller requirements for computational resources (memory and runtime).","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132275995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Effects of critically damped total PDN impedance in chip-package-board co-design 临界阻尼总PDN阻抗对芯片封装板协同设计的影响

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351674

R. Kobayashi, G. Kubo, H. Otsuka, T. Mido, Y. Kobayashi, H. Fujii, T. Sudo

{"title":"Effects of critically damped total PDN impedance in chip-package-board co-design","authors":"R. Kobayashi, G. Kubo, H. Otsuka, T. Mido, Y. Kobayashi, H. Fujii, T. Sudo","doi":"10.1109/ISEMC.2012.6351674","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351674","url":null,"abstract":"As CMOS LSIs operate at higher clock frequency and at lower supply voltage, power integrity is becoming a critical issue to maintain digital electronic systems more stable. Power supply fluctuation excited by core circuits or I/O circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be taking into consideration in the chip-package-board co-design. Especially, anti-resonance peaks in the PDN due to the parallel combination of on-chip capacitance and package inductance induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by designing different on-chip PDN properties. The measured power supply noises for the four test chips successfully showed typical characteristics of 3 different regions. The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on a chip.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133030671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Feasibility of fault analysis based on intentional electromagnetic interference 基于故意电磁干扰的故障分析的可行性

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351665

J. Takahashi, Yu-ichi Hayashi, N. Homma, H. Fuji, T. Aoki

{"title":"Feasibility of fault analysis based on intentional electromagnetic interference","authors":"J. Takahashi, Yu-ichi Hayashi, N. Homma, H. Fuji, T. Aoki","doi":"10.1109/ISEMC.2012.6351665","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351665","url":null,"abstract":"This paper presents the feasibility of fault analysis using intentional electromagnetic interference (IEMI). Fault analysis (FA) is a kind of implementation attack that intentionally extracts a secret key embedded in a secure device such as a smart card. An attacker injects a computational fault during the cryptographic calculation and he can extract a secret key. Recently, Hayashi et al. showed that temporal faults could be remotely injected during the cryptographic calculation using IEMI. They showed a case study in which an Advanced Standard Encryption (AES) secret key could be extracted through fault analysis. However, the characteristics of faults that can be induced by IEMI were not described. And, a threat of various FAs was not clear. In this paper, we examine in detail how the IEMI fault injection affects the fault occurrence of intermediate states in a cryptographic module and investigate the distribution of the IEMI generated faults. Furthermore, we classify previous FAs with respect to an attack model such as the type of faults needed to achieve a successful attack, and discuss the feasibility of FAs using IEMI based on the experimental results.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115167124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Modeling of coupled TSVs in 3D ICs 三维集成电路中耦合tsv的建模

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351759

Ege Engin, Srinidhi Raghavan

引用次数: 4

ASIC package design optimization for 10 Gbps and above backplane serdes links 针对10gbps及以上背板服务器链路的ASIC封装设计优化

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351784

J. Lim, K. Chow, Ji Zhang, Jianmin Zhang, K. Qiu, R. Brooks

{"title":"ASIC package design optimization for 10 Gbps and above backplane serdes links","authors":"J. Lim, K. Chow, Ji Zhang, Jianmin Zhang, K. Qiu, R. Brooks","doi":"10.1109/ISEMC.2012.6351784","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351784","url":null,"abstract":"This paper discussed the package selection and BGA signal pin assignment consideration for high-end ASIC design with over 400 SerDes (Serializer Deserializer) pairs for >;10Gbps backplane interface. The ASIC package is using advanced high-performance organic build-up (BU) materials like GX13, GZ41 and thinner core in the stack-up to help reduce the package loss and improve the signal transmission on the highspeed SerDes links. For return loss and insertion loss studies, the main objectives are to investigate the core thickness, BU material properties, and routing configurations impact on the differential signalling. The design suggestions are then made at each area for performance and cost optimization. For crosstalk studies, various pin-out patterns for transmit to transmit or receive to receive signals, and transmit to receive signals, have been designed and studied to investigate signal coupling and PCB escape routing requirements. Both frequency and time domain simulations are performed to compare the signal isolation performance. The most optimized pin-out is then selected to achieve the overall required system performance. Lastly, various package substrate samples with different BU materials, core thicknesses and crosstalk structures are manufactured to validate package design performance using probe station technique.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":"44 11-12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125243186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Critical EMC test issues needing early resolution 需要尽早解决的关键EMC测试问题

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351797

C. B. White

引用次数: 4

Prediction of common-mode current reduction using ferrites in systems with cable harnesses 用铁氧体预测电缆线束系统的共模电流减小

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351807

N. Bondarenko, Peng Shao, A. Orlando, M. Koledintseva, D. Beetner, P. Berger

引用次数: 3