2012 IEEE International Symposium on Electromagnetic Compatibility最新文献_第3页

On-chip design techniques for reducing power supply noise effects on ADC with chip-PCB hierarchical structure 芯片- pcb层次化结构降低ADC电源噪声影响的片上设计技术

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351672

Bumhee Bae, Jonghyun Cho, Joungho Kim

{"title":"On-chip design techniques for reducing power supply noise effects on ADC with chip-PCB hierarchical structure","authors":"Bumhee Bae, Jonghyun Cho, Joungho Kim","doi":"10.1109/ISEMC.2012.6351672","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351672","url":null,"abstract":"In this paper, we propose the on-chip design techniques for controlling Power Supply Noise (PSN) effects on Analog-to-Digital Converter (ADC) with chip-Printed Circuit Board (PCB) hierarchical structure interconnected by bonding wires. There are two steps for explaining the proposed design technique. First, we explain what the PSN coupling path is on ADC. The PSN will couple from noise source to noise victim via power distribution network and circuit path. Second, we propose how we can reduce the noise coupling effects. The comparator is essential circuit to ADC and most sensitive circuit to PSN in ADC. Therefore, it is important to reduce the noise coupling effects on comparator for designing ADC which is non-sensitive to PSN. The comparator has two input nodes, and the differential voltage between two input nodes affect to ADC output. The impedance imbalance between two comparator inputs is the reason why the comparator is sensitive to PSN. So, the technique which is for balancing two input impedance is important to reduce PSN effects. We consider chip-PCB components to estimate two input impedance, because the two input impedances are affected by chip-PCB hierarchical structure. If we control the impedance of each input, we can design the ADC which is nonsensitive to PSN at the targeted frequency. We demonstrate the proposed technique based on simulation by PSN whose frequency swept from 1MHz to 3GHz.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134644979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Overview of the threat of IEMI (intentional electromagnetic interference) IEMI(故意电磁干扰)威胁概述

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351829

E. Savage, W. Radasky

引用次数: 28

Feasibility of fault analysis based on intentional electromagnetic interference 基于故意电磁干扰的故障分析的可行性

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351665

J. Takahashi, Yu-ichi Hayashi, N. Homma, H. Fuji, T. Aoki

{"title":"Feasibility of fault analysis based on intentional electromagnetic interference","authors":"J. Takahashi, Yu-ichi Hayashi, N. Homma, H. Fuji, T. Aoki","doi":"10.1109/ISEMC.2012.6351665","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351665","url":null,"abstract":"This paper presents the feasibility of fault analysis using intentional electromagnetic interference (IEMI). Fault analysis (FA) is a kind of implementation attack that intentionally extracts a secret key embedded in a secure device such as a smart card. An attacker injects a computational fault during the cryptographic calculation and he can extract a secret key. Recently, Hayashi et al. showed that temporal faults could be remotely injected during the cryptographic calculation using IEMI. They showed a case study in which an Advanced Standard Encryption (AES) secret key could be extracted through fault analysis. However, the characteristics of faults that can be induced by IEMI were not described. And, a threat of various FAs was not clear. In this paper, we examine in detail how the IEMI fault injection affects the fault occurrence of intermediate states in a cryptographic module and investigate the distribution of the IEMI generated faults. Furthermore, we classify previous FAs with respect to an attack model such as the type of faults needed to achieve a successful attack, and discuss the feasibility of FAs using IEMI based on the experimental results.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115167124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Critical EMC test issues needing early resolution 需要尽早解决的关键EMC测试问题

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351797

C. B. White

引用次数: 4

ASIC package design optimization for 10 Gbps and above backplane serdes links 针对10gbps及以上背板服务器链路的ASIC封装设计优化

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351784

J. Lim, K. Chow, Ji Zhang, Jianmin Zhang, K. Qiu, R. Brooks

{"title":"ASIC package design optimization for 10 Gbps and above backplane serdes links","authors":"J. Lim, K. Chow, Ji Zhang, Jianmin Zhang, K. Qiu, R. Brooks","doi":"10.1109/ISEMC.2012.6351784","DOIUrl":"https://doi.org/10.1109/ISEMC.2012.6351784","url":null,"abstract":"This paper discussed the package selection and BGA signal pin assignment consideration for high-end ASIC design with over 400 SerDes (Serializer Deserializer) pairs for >;10Gbps backplane interface. The ASIC package is using advanced high-performance organic build-up (BU) materials like GX13, GZ41 and thinner core in the stack-up to help reduce the package loss and improve the signal transmission on the highspeed SerDes links. For return loss and insertion loss studies, the main objectives are to investigate the core thickness, BU material properties, and routing configurations impact on the differential signalling. The design suggestions are then made at each area for performance and cost optimization. For crosstalk studies, various pin-out patterns for transmit to transmit or receive to receive signals, and transmit to receive signals, have been designed and studied to investigate signal coupling and PCB escape routing requirements. Both frequency and time domain simulations are performed to compare the signal isolation performance. The most optimized pin-out is then selected to achieve the overall required system performance. Lastly, various package substrate samples with different BU materials, core thicknesses and crosstalk structures are manufactured to validate package design performance using probe station technique.","PeriodicalId":197346,"journal":{"name":"2012 IEEE International Symposium on Electromagnetic Compatibility","volume":"44 11-12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125243186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Prediction of common-mode current reduction using ferrites in systems with cable harnesses 用铁氧体预测电缆线束系统的共模电流减小

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351807

N. Bondarenko, Peng Shao, A. Orlando, M. Koledintseva, D. Beetner, P. Berger

引用次数: 3

Modeling of coupled TSVs in 3D ICs 三维集成电路中耦合tsv的建模

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351759

Ege Engin, Srinidhi Raghavan

引用次数: 4

Simulation geometry rasterization for applications toward graphene interconnect characterization 用于石墨烯互连表征的模拟几何光栅化应用

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351813

B. Rautio, Qiang Long, A. Agrawal, M. E. El Sabbagh

引用次数: 1

Time domain E-PMCHW integral equation solved by adaptive marching-on-in-order procedure for predicting transient responses of some composite structures 用自适应序进法求解时域E-PMCHW积分方程，预测复合材料结构的瞬态响应

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6351677

Jian-Yao Zhao, W. Yin, Ming-da Zhu, W. Luo

引用次数: 1

Human exposure in arc-welding processes: Current versus previous ICNIRP basic restrictions 弧焊过程中的人体暴露:当前与以前的ICNIRP基本限制

2012 IEEE International Symposium on Electromagnetic Compatibility Pub Date : 2012-11-12 DOI: 10.1109/ISEMC.2012.6350920

F. Grassi, G. Spadacini, S. Pignari

引用次数: 1