发布求助
文献互助 智能选刊 最新文献

Proceedings VHDL International Users Forum Fall Workshop最新文献

筛选
英文 中文
Mixed language design data access: procedural interface design considerations 混合语言设计数据访问:过程接口设计注意事项
Proceedings VHDL International Users Forum Fall Workshop Pub Date : 2000-10-18 DOI: 10.1109/VIUF.2000.890276
Françoise Martinolle, U. Parvathy
{"title":"Mixed language design data access: procedural interface design considerations","authors":"Françoise Martinolle, U. Parvathy","doi":"10.1109/VIUF.2000.890276","DOIUrl":"https://doi.org/10.1109/VIUF.2000.890276","url":null,"abstract":"A procedural language interface allows access of static and runtime data. With mixed language design becoming more prevalent, comes the necessity to develop bilingual procedural language interfaces. What is the best approach? Extend an existing HDL interface to deal with the other language, provide a language-independent interface, or create a dual interface? This paper discusses the different approaches and describes the solution chosen to develop a Verilog/VHDL language interface.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123606218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Testing a procedural interface for conformance to a standard 测试程序接口是否符合标准
Proceedings VHDL International Users Forum Fall Workshop Pub Date : 2000-10-18 DOI: 10.1109/VIUF.2000.890275
U. Parvathy, Françoise Martinolle, S. Subramanian
{"title":"Testing a procedural interface for conformance to a standard","authors":"U. Parvathy, Françoise Martinolle, S. Subramanian","doi":"10.1109/VIUF.2000.890275","DOIUrl":"https://doi.org/10.1109/VIUF.2000.890275","url":null,"abstract":"Procedural interface testing is a complex task since it requires in-depth knowledge in more than one domain. In particular, testing procedural interfaces (PI) to HDL simulators require knowledge of both programming and HDL modeling. This paper describes a methodology to automatically generate a test suite from a formal model specification of a HDL procedural interface. Since this test program is generated automatically from the formal model, it is correct by construction. Therefore an error encountered during the testing indicates either a problem in the PI implementation or in the formal model specification.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"363 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122829404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Gated clocks in RT-synthesis and simulation rt合成与仿真中的门控时钟
Proceedings VHDL International Users Forum Fall Workshop Pub Date : 2000-10-18 DOI: 10.1109/VIUF.2000.890269
W. Ecker, A. Windisch, J. Mades, T. Schneider, Ke Yang
{"title":"Gated clocks in RT-synthesis and simulation","authors":"W. Ecker, A. Windisch, J. Mades, T. Schneider, Ke Yang","doi":"10.1109/VIUF.2000.890269","DOIUrl":"https://doi.org/10.1109/VIUF.2000.890269","url":null,"abstract":"The paper discusses several alternatives for dealing with the simulation mismatch resulting from partially gating clocks in RT-descriptions. Currently synthesizable approaches as clock delta balancing and simulation time delay of combinatorial assignments are first discussed. Local clock gate descriptions based on wait statements and global clock gate descriptions based on guards are then presented. Finally, an extension of the VHDL port map towards type conversion functions with more than one (signal)-parameter is proposed.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"355 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120893860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On upgrading legacy electronics systems: methodology, enabling technologies and tools 关于升级传统电子系统:方法、使能技术和工具
Proceedings VHDL International Users Forum Fall Workshop Pub Date : 2000-10-18 DOI: 10.1109/VIUF.2000.890178
Vijay K. Madisetti, Yong-Kyu Jung, M. Khan, J. Kim, T. Finnessy
{"title":"On upgrading legacy electronics systems: methodology, enabling technologies and tools","authors":"Vijay K. Madisetti, Yong-Kyu Jung, M. Khan, J. Kim, T. Finnessy","doi":"10.1109/VIUF.2000.890178","DOIUrl":"https://doi.org/10.1109/VIUF.2000.890178","url":null,"abstract":"Defense and commercial electronics systems need upgrading for a number of reasons; obsolete parts, diminishing manufacturing sources (DMS), availability of newer technologies that are superior to older ones, requirements for newer functionality and form-fit-function replacements, in addition to the drive towards using commercial-off-the-shelf (COTS) technology. We propose a comprehensive methodology and a set of enabling technologies that facilitate the efficient recovery of legacy component and system functionality, tradeoff-based redesign and functional replacement, followed by synthesis and test of the upgraded system (consisting of hardware and software). Our VHDL-based methodology is currently being evaluated on several avionics programs under the auspices of the Air Force Electronics Parts Obsolescence Initiative (EPOI), and some recent results are presented.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126125264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Predicting the performance of SoC verification technologies 预测SoC验证技术的性能
Proceedings VHDL International Users Forum Fall Workshop Pub Date : 2000-10-18 DOI: 10.1109/VIUF.2000.890258
G. D. Peterson
{"title":"Predicting the performance of SoC verification technologies","authors":"G. D. Peterson","doi":"10.1109/VIUF.2000.890258","DOIUrl":"https://doi.org/10.1109/VIUF.2000.890258","url":null,"abstract":"Verification demands for system on chip (SoC) design looms as one of the most significant challenges to designers. With the substantial costs and increasing importance of system verification technologies, determining the best verification strategy is critical to SoC design and business success. The paper focuses on how a designer can apply a model to perform tradeoffs between the different types of emulation, hardware acceleration, and simulation verification tools available. The predictive power of the modeling approach is applied to usage scenarios to determine the most appropriate verification strategy to employ in current or future SoC development efforts.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116297612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Requirements modeling technology: a vision for better, faster, and cheaper systems 需求建模技术:对更好、更快、更便宜的系统的展望
Proceedings VHDL International Users Forum Fall Workshop Pub Date : 2000-10-18 DOI: 10.1109/VIUF.2000.890177
darrell. barker
{"title":"Requirements modeling technology: a vision for better, faster, and cheaper systems","authors":"darrell. barker","doi":"10.1109/VIUF.2000.890177","DOIUrl":"https://doi.org/10.1109/VIUF.2000.890177","url":null,"abstract":"The paper discusses a vision, motivation, and objectives for a new engineering technology based on the Rosetta System Level Design Language (SLDL) that we call \"requirements modeling\". Requirements modeling is what systems engineers and systems analysts do with Rosetta SLDL. Rosetta SLDL is information technology that supports the specification of multi-technology, multifaceted, multi-discipline systems. Until the Rosetta SLDL emerged, no good way existed to help the design team \"get its arms around\" all of the requirements for a complex system. Requirements related issues are the most common source of systems engineering problems and they impact all aspects of product development. Requirements models help design teams stay \"on the same page\" with each other. Requirements modeling reduces cycle time, reduces costs, reduces the probability of overruns, and helps with support and sustainment of the product. Requirements models will be the input to many new and enhanced design automation tools and processes. The benefits of requirements modeling technology are wide reaching, because system requirements touch everything and everyone associated with a product.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"470 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116517807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Automated test vector generation from Rosetta requirements 根据Rosetta需求自动生成测试向量
Proceedings VHDL International Users Forum Fall Workshop Pub Date : 2000-10-18 DOI: 10.1109/VIUF.2000.890263
K. Ranganathan, M. Rangarajan, P. Alexander, T. Regan
{"title":"Automated test vector generation from Rosetta requirements","authors":"K. Ranganathan, M. Rangarajan, P. Alexander, T. Regan","doi":"10.1109/VIUF.2000.890263","DOIUrl":"https://doi.org/10.1109/VIUF.2000.890263","url":null,"abstract":"Formal high-level specifications are increasingly being used when designing systems. There are a number of advantages to this approach, an important one being the validation of the system against the original specifications. This aspect of specifications gains increasing importance as the designers design systems at higher levels of abstraction. From initial designs at these high levels of abstraction, the system goes through many stages of refinement before finally emerging as a product. Therefore, it is critical to ensure that the final product is what was first intended to be built. We describe an automated approach to validating systems using axiomatic specifications and simulation. Specifically, we describe the generation of test scenarios from Rosetta specifications, which are then combined with test requirements to generate abstract test vectors. These abstract test vectors can directly be translated to specific inputs to simulation runs, and the outputs generated during these runs can be checked against the acceptance criteria generated from the specifications.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133709403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Another approach to system level design 这是系统级设计的另一种方法
Proceedings VHDL International Users Forum Fall Workshop Pub Date : 2000-10-18 DOI: 10.1109/VIUF.2000.890259
Y. Veller
{"title":"Another approach to system level design","authors":"Y. Veller","doi":"10.1109/VIUF.2000.890259","DOIUrl":"https://doi.org/10.1109/VIUF.2000.890259","url":null,"abstract":"The paper presents VisualSLD, a system design and simulation tool with an innovative computational model that tries to bridge the classic system design approach and the HDL design approach, and integrate both into a coherent framework. The paper presents the computational model and gives an example of high-level system design and transition to hardware design.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123843999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A VHDL success story: electric drive system using neural controller 一个VHDL的成功案例:使用神经控制器的电驱动系统
Proceedings VHDL International Users Forum Fall Workshop Pub Date : 2000-10-18 DOI: 10.1109/VIUF.2000.890280
M. Cirstea, A. Dinu, M. McCormick, D. Nicula
{"title":"A VHDL success story: electric drive system using neural controller","authors":"M. Cirstea, A. Dinu, M. McCormick, D. Nicula","doi":"10.1109/VIUF.2000.890280","DOIUrl":"https://doi.org/10.1109/VIUF.2000.890280","url":null,"abstract":"This article describes the successful VHDL design of a digital current control architecture for three phase electric drive systems, based on hardware implemented neural networks. The controller comprises an on-line inductance estimator and a PWM switching pattern generator based on a state space observer. Reconfigurable neural networks implemented with logic gates are involved in both. The complete development of the system has been achieved using VHDL and implemented into a single FPGA chip. The VHDL description of the neural networks has been automatically generated by C++ programs. The VHDL model of the motor controller allows the control over the hardware implementation complexity and therefore it can be readily adapted to the available hardware resources.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131207611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
High-level test generation from VHDL behavioral descriptions 从VHDL行为描述生成高级测试
Proceedings VHDL International Users Forum Fall Workshop Pub Date : 2000-10-18 DOI: 10.1109/VIUF.2000.890282
A. Gharebaghi, Z. Navabi
{"title":"High-level test generation from VHDL behavioral descriptions","authors":"A. Gharebaghi, Z. Navabi","doi":"10.1109/VIUF.2000.890282","DOIUrl":"https://doi.org/10.1109/VIUF.2000.890282","url":null,"abstract":"In this paper a method for high-level test generation for systems described in VHDL is presented. First, two test generation algorithms for VHDL processes are presented. The first algorithm works on processes which represent combinational logic whereas the second works on processes which represent sequential logic. The goal of both algorithms is to test all portions of the process body by traversing all the feasible paths. Employing these two algorithms, two new algorithms for system-level test generation for both combinational and sequential systems are presented. The approach employs software metrics as well as signal coverage for interconnections and state and transition coverage for FSMs.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130273391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书