{"title":"Modeling foreign architectures with VHPI","authors":"J. Shields","doi":"10.1109/VIUF.2000.890278","DOIUrl":"https://doi.org/10.1109/VIUF.2000.890278","url":null,"abstract":"VHPI is the VHDL Procedural Interface, an IEEE standards effort, with an ANSI C interface for developing models and applications that are easily integrated into a compliant simulation tool. VHPI provides sufficient access to the runtime data model to implement foreign architectures equivalent to those which can be described in VHDL. This paper examines how the control and data flow features of VHPI can be used for modeling foreign architectures.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131654959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"HDML: compiled VHDL in XML","authors":"M. Reshadi, B. Goji-Ara, Z. Navabi","doi":"10.1109/VIUF.2000.890270","DOIUrl":"https://doi.org/10.1109/VIUF.2000.890270","url":null,"abstract":"Communication between designers and tools is a necessity and plays a significant role in productivity and time to market. XML, as an emerging standard, has proved to be a very suitable format for exchanging data on network and between applications. In addition, there are many public-domain tools for manipulating data in XML format regardless of what that data represents. HDML (Hardware Description Markup Language) is a new model for representing compiled data from original VHDL code in XML format. In addition to benefiting from XML advantages, HDML also develops a powerful mechanism for rule checking on a compiled design model. Although, the model does not depend on a specific data structure, we have used a revised version of ATRE/CE for developing an analyzer for converting VHDL to HDML. To illustrate the capabilities of HDML, this paper discusses an example application of our XML based intermediate format, which is typical of many other potential applications. This specific application checks syntax and semantics of an input VHDL code for synthesis and we refer to is as the synthesizability rule checker.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124610786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Karayiannis, J. Mades, T. Schneider, A. Windisch, W. Ecker
{"title":"Using XML for representation and visualization of elaborated VHDL-AMS models","authors":"T. Karayiannis, J. Mades, T. Schneider, A. Windisch, W. Ecker","doi":"10.1109/VIUF.2000.890273","DOIUrl":"https://doi.org/10.1109/VIUF.2000.890273","url":null,"abstract":"The paper presents a newly developed XML intermediate for fully elaborated VHDL-AMS designs. The intermediate contains both complete static-semantic information inherent to VHDL-AMS and dynamic, simulation-related information, such as the current values of signal drivers or the dynamic equation sets. Therefore the intermediate can be used for the development of VHDL-AMS related applications. The presented XML intermediate was successfully used for HTML export of design structures.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121606046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Cesário, L. Gauthier, D. Lyonnard, Gabriela Nicolescu, A. Jerraya
{"title":"An XML-based meta-model for the design of multiprocessor embedded systems","authors":"W. Cesário, L. Gauthier, D. Lyonnard, Gabriela Nicolescu, A. Jerraya","doi":"10.1109/VIUF.2000.890272","DOIUrl":"https://doi.org/10.1109/VIUF.2000.890272","url":null,"abstract":"The design of multiprocessor embedded systems requires new design paradigms. Most new paradigms are conceived around the idea of deploying pre-characterized software and hardware components. Making all these building blocks communicate in an efficient and error-proof manner is the most important challenge facing new design methodologies. Expectably, convenient modeling of these components and their communication at different abstraction levels is the central problem of any new system-level synthesis environment. We present Colif, a meta-model that was developed to be an object-oriented intermediate design model for system-level synthesis of multiprocessor embedded systems. Its design representation clearly distinguishes communication infrastructure and behavior, allowing independent refinement of these features. Colif objects are polymorphic, in the sense that they represent design information at different abstraction levels. At the highest abstraction level, it does not impose any specific computation model or communication semantics, it could be seen as a \"meta-model\". It will only have full execution semantics, so we could call it an \"actual\" design model, when working at lower abstraction levels.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"11 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123493899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Cirstea, A. Aounis, M. McCormick, P. Urwin, L. Haydock
{"title":"Induction motor drive system modelled in VHDL","authors":"M. Cirstea, A. Aounis, M. McCormick, P. Urwin, L. Haydock","doi":"10.1109/VIUF.2000.890279","DOIUrl":"https://doi.org/10.1109/VIUF.2000.890279","url":null,"abstract":"The paper presents a new approach to the modelling, simulation and controller design of a complete induction motor electric drive system. The novel technique uses a hardware description language (VHDL) as a unique EDA environment for the system modelling, evaluation and controller design. Simulation results are presented, proving the validity of the model for the vector controlled induction motor system. The advantages of the VHDL approach for a complete drive modelling and control strategy implementation are underlined.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125891759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}