{"title":"测试程序接口是否符合标准","authors":"U. Parvathy, Françoise Martinolle, S. Subramanian","doi":"10.1109/VIUF.2000.890275","DOIUrl":null,"url":null,"abstract":"Procedural interface testing is a complex task since it requires in-depth knowledge in more than one domain. In particular, testing procedural interfaces (PI) to HDL simulators require knowledge of both programming and HDL modeling. This paper describes a methodology to automatically generate a test suite from a formal model specification of a HDL procedural interface. Since this test program is generated automatically from the formal model, it is correct by construction. Therefore an error encountered during the testing indicates either a problem in the PI implementation or in the formal model specification.","PeriodicalId":192334,"journal":{"name":"Proceedings VHDL International Users Forum Fall Workshop","volume":"363 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Testing a procedural interface for conformance to a standard\",\"authors\":\"U. Parvathy, Françoise Martinolle, S. Subramanian\",\"doi\":\"10.1109/VIUF.2000.890275\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Procedural interface testing is a complex task since it requires in-depth knowledge in more than one domain. In particular, testing procedural interfaces (PI) to HDL simulators require knowledge of both programming and HDL modeling. This paper describes a methodology to automatically generate a test suite from a formal model specification of a HDL procedural interface. Since this test program is generated automatically from the formal model, it is correct by construction. Therefore an error encountered during the testing indicates either a problem in the PI implementation or in the formal model specification.\",\"PeriodicalId\":192334,\"journal\":{\"name\":\"Proceedings VHDL International Users Forum Fall Workshop\",\"volume\":\"363 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-10-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings VHDL International Users Forum Fall Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VIUF.2000.890275\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings VHDL International Users Forum Fall Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VIUF.2000.890275","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Testing a procedural interface for conformance to a standard
Procedural interface testing is a complex task since it requires in-depth knowledge in more than one domain. In particular, testing procedural interfaces (PI) to HDL simulators require knowledge of both programming and HDL modeling. This paper describes a methodology to automatically generate a test suite from a formal model specification of a HDL procedural interface. Since this test program is generated automatically from the formal model, it is correct by construction. Therefore an error encountered during the testing indicates either a problem in the PI implementation or in the formal model specification.