VIII IEEE International Power Electronics Congress, 2002. Technical Proceedings. CIEP 2002.最新文献

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Robust sliding mode control for the boost converter 升压变换器的鲁棒滑模控制
D. Cortés, J. Alvarez, J. Alvarez
{"title":"Robust sliding mode control for the boost converter","authors":"D. Cortés, J. Alvarez, J. Alvarez","doi":"10.1109/CIEP.2002.1216661","DOIUrl":"https://doi.org/10.1109/CIEP.2002.1216661","url":null,"abstract":"The sliding mode control of the boost converter is revisited. Several sliding surfaces are presented and analyzed. Some of the surfaces presented do not depend on the circuit load, eliminating the necessity to measure the current measurement. The analysis presented is based on the switching model of the circuit instead of the average model typically used. Practical aspects for implementing sliding mode controller with the proposed surfaces are discussed.","PeriodicalId":191010,"journal":{"name":"VIII IEEE International Power Electronics Congress, 2002. Technical Proceedings. CIEP 2002.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126655798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Generation of noncharacteristics harmonics generated by adjustable speed drives 变速驱动产生的非特征谐波的产生
M. Contreras, H. Calleja, V. Cardenas
{"title":"Generation of noncharacteristics harmonics generated by adjustable speed drives","authors":"M. Contreras, H. Calleja, V. Cardenas","doi":"10.1109/CIEP.2002.1216639","DOIUrl":"https://doi.org/10.1109/CIEP.2002.1216639","url":null,"abstract":"The generation of the noncharacteristics harmonics in AC supply feeding adjustable speed drives is experimentally investigated, taking into account the effect of the modulation index, the DC filter cutoff frequency and the output frequency of the inverter. Test performed included a single ASD connected to the mains, two inverters connected to the DC link and two ASDs connected to the grid, all under balanced supply and load. The behavior with an unbalanced supply and balanced load is also reported.","PeriodicalId":191010,"journal":{"name":"VIII IEEE International Power Electronics Congress, 2002. Technical Proceedings. CIEP 2002.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114396168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel MTO-design based on silicon-silicon bonding 基于硅-硅键合的新型mto设计
D. Detjen, S. Schroder, T. Plum, R. D. De Doncker
{"title":"Novel MTO-design based on silicon-silicon bonding","authors":"D. Detjen, S. Schroder, T. Plum, R. D. De Doncker","doi":"10.1109/CIEP.2002.1216632","DOIUrl":"https://doi.org/10.1109/CIEP.2002.1216632","url":null,"abstract":"A new MOS-turn-off thyristor (MTO) device structure is proposed which is based on the silicon-silicon bonding technology. The basic idea is to connect several p-channel power-MOSFETs with a 3-layer bipolar structure. The 3-layer structure corresponds to the pnp-transistor structure of classical thyristors. It can be manufactured as a disc-type device. During the MTO on-state the current is flowing through the reverse conducting diode of the MOSFET structure. Hence, the n-well of the MOSFETs represents the cathode of the thyristor. The device is turned off with unity-gain by switching on the p-channel to bypass the cathode-side pn-junction. Thus, the device operates like a fully integrated MTO but avoids the technological restrictions in manufacturing VLSI-structures on disc-type devices. In contrast to the conventional hybrid MTO, the device can be also turned on by the MOS gate. The capacitive gate current of the MOSFETs enables an extremely homogeneous latching behavior of the thyristor structure. Finite element simulations have been performed including a physical model of the bonding interface. The results are showing very promising device characteristics.","PeriodicalId":191010,"journal":{"name":"VIII IEEE International Power Electronics Congress, 2002. Technical Proceedings. CIEP 2002.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128316130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Flyback-based PFC converter with sinusoidal output for use in AC UPS 用于交流UPS的正弦输出反激式PFC变换器
J. Hoyo, J. Arau, C. Aguilar, E. Martínez
{"title":"Flyback-based PFC converter with sinusoidal output for use in AC UPS","authors":"J. Hoyo, J. Arau, C. Aguilar, E. Martínez","doi":"10.1109/CIEP.2002.1216656","DOIUrl":"https://doi.org/10.1109/CIEP.2002.1216656","url":null,"abstract":"Nowadays, the number of sensitive loads connected to the utility line increases fast. These loads need a highly reliable power supply. One way to provide this kind of energy is using an uninterruptible power supply (UPS). Basically, a UPS providing input power factor correction (PFC) is a three stage system: PFC stage, DC-DC converter stage and inverter stage. The approach proposed eliminates the DC-DC converter stage and removes the bulk capacitor of the PFC stage to use the natural output waveform of the converter before filtering: a semisinusoidal waveform. This allows the inverter stage working at low frequency with high efficiency. The PFC stage is based on a flyback topology operating in DCM to have a simple control loop.","PeriodicalId":191010,"journal":{"name":"VIII IEEE International Power Electronics Congress, 2002. Technical Proceedings. CIEP 2002.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121694116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An adaptive controller for a series active filter to compensate voltage sags, unbalance and harmonic distortion 一种用于补偿电压跌落、不平衡和谐波畸变的串联有源滤波器自适应控制器
G. Escobar, A. Stanković, V. Cárdenas, P. Mattavelli
{"title":"An adaptive controller for a series active filter to compensate voltage sags, unbalance and harmonic distortion","authors":"G. Escobar, A. Stanković, V. Cárdenas, P. Mattavelli","doi":"10.1109/CIEP.2002.1216672","DOIUrl":"https://doi.org/10.1109/CIEP.2002.1216672","url":null,"abstract":"In this paper we present an adaptive controller for the series active filter to guarantee a sinusoidal balanced voltage on the load side despite of the presence of perturbations in the source voltage such as unbalance, harmonic distortion, sags and swells, as well as disturbances in the current load such as step changes, unbalance and distortion by higher order harmonics. To accomplish this objective, the series active filter is forced to inject the appropriate voltage to the line through a series connected transformer. This task is performed by the proposed controller in three stages (loops). First, an inner control loop forces the injected voltage to track a periodic reference. Second, an outer control loop regulates the voltage level in the capacitor (the storage element) making possible the construction of such a periodic reference. Third, the power flow between the line and the DC capacitor is handled by an outer (higher level) loop that allows the DC capacitor to deliver or to absorb the necessary power to improve transients on load voltage when changes appear in the active power delivered by the source or absorbed by the load.","PeriodicalId":191010,"journal":{"name":"VIII IEEE International Power Electronics Congress, 2002. Technical Proceedings. CIEP 2002.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126901159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High power factor pre-regulator with high efficiency 高效率的高功率因数预调节器
N. Vázquez, O. Lopez, C. Hernández, E. Rodríguez, J. Arau
{"title":"High power factor pre-regulator with high efficiency","authors":"N. Vázquez, O. Lopez, C. Hernández, E. Rodríguez, J. Arau","doi":"10.1109/CIEP.2002.1216668","DOIUrl":"https://doi.org/10.1109/CIEP.2002.1216668","url":null,"abstract":"In this paper a high power factor pre-regulator with high efficiency is presented. In the proposed scheme one converter is used, but it does not process all the power delivered to the load. The power is processed less than once, resulting in an efficient converter. The proposed pre-regulator can be used with a traditional regulator or a regulator with improved efficiency, resulting that the power is processed one and half times or less than once respectively. Analysis, simulation and experimental results of the converter are presented.","PeriodicalId":191010,"journal":{"name":"VIII IEEE International Power Electronics Congress, 2002. Technical Proceedings. CIEP 2002.","volume":"744 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132093779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cascade multilevel inverter with only one DC source 只有一个直流电源的级联多电平逆变器
E. Bircenas, S. Ramirez, V. Cárdenas, R. Echavarría
{"title":"Cascade multilevel inverter with only one DC source","authors":"E. Bircenas, S. Ramirez, V. Cárdenas, R. Echavarría","doi":"10.1109/CIEP.2002.1216655","DOIUrl":"https://doi.org/10.1109/CIEP.2002.1216655","url":null,"abstract":"Multilevel converters are a very interesting solution for medium and high voltage applications. Because of its characteristic of synthesizing a sinusoidal voltage on several DC levels. The better topology for power quality and transmission systems applications is the cascade multilevel inverters. However, this topology presents a problem that consists in the use of several DC sources. This paper presents a solution to this problem, maintaining the advantages that offer multilevel topologies, such as, high quality in the output voltage and low voltages stress in the devices. Simulation and experimental results are also included.","PeriodicalId":191010,"journal":{"name":"VIII IEEE International Power Electronics Congress, 2002. Technical Proceedings. CIEP 2002.","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115759539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
A large-signal model for the PRC-LCC resonant topology with a capacitor as output filter 以电容作为输出滤波器的PRC-LCC谐振拓扑的大信号模型
J. Martín-Ramos, J. Díaz, A. Pernía, M. Prieto, F. Linera
{"title":"A large-signal model for the PRC-LCC resonant topology with a capacitor as output filter","authors":"J. Martín-Ramos, J. Díaz, A. Pernía, M. Prieto, F. Linera","doi":"10.1109/CIEP.2002.1216636","DOIUrl":"https://doi.org/10.1109/CIEP.2002.1216636","url":null,"abstract":"In this paper, two mathematical models are presented to approximate, accurately enough, the large signal dynamical behaviour and the steady state behaviour of the PRC-LCC resonant topology with a capacitor as output filter. The method used to obtain these models is based on applying of the extended describing function and the generalised averaging modelling techniques. Therefore, the evolution of the topology waveforms, most of them sinusoidal, is approximated by their corresponding envelope. These envelopes are expressed by a set of nonlinear differential equations which are solved numerically with the help of a computer. The resulting algorithm is faster than a straight PSpice simulation and free of convergence problems. Finally, the good concordance between the models and the practice is verified with a wide set of experimental results.","PeriodicalId":191010,"journal":{"name":"VIII IEEE International Power Electronics Congress, 2002. Technical Proceedings. CIEP 2002.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124260454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
SPICE modelling of PWM controllers PWM控制器的SPICE建模
J. Zarebski, K. Górecki
{"title":"SPICE modelling of PWM controllers","authors":"J. Zarebski, K. Górecki","doi":"10.1109/CIEP.2002.1216637","DOIUrl":"https://doi.org/10.1109/CIEP.2002.1216637","url":null,"abstract":"In the paper the problem of electrothermal modelling of PWM controllers for SPICE is considered. SPICE library macromodel and a new form of the authors' electrothermal macromodel of SG3525A controller are presented. To illustrate the correctness and usefulness of these macromodels, some results of measurements and calculations of SG3525A controller, operating in catalogue test circuit and in the real boost converter are given as well.","PeriodicalId":191010,"journal":{"name":"VIII IEEE International Power Electronics Congress, 2002. Technical Proceedings. CIEP 2002.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115917025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The parallel active input current shaper 并联有源输入电流整形器
C. Hernández, J. López, N. Vázquez, E. Rodríguez, J. Arau
{"title":"The parallel active input current shaper","authors":"C. Hernández, J. López, N. Vázquez, E. Rodríguez, J. Arau","doi":"10.1109/CIEP.2002.1216669","DOIUrl":"https://doi.org/10.1109/CIEP.2002.1216669","url":null,"abstract":"Several approaches have been presented in order to meet the power quality regulations maintaining the lowest number of components with the purpose of minimize the cost and complexity. In this paper a new active input current shaper (AICS) is presented. In difference with the traditional series AICS, the proposed scheme connects the auxiliary output of the main converter in parallel of the rectified AC mains. The proposed parallel scheme demands a current with a low harmonic content that the standard specifications are fulfilled. The operation, simulation and experimental results of the proposed scheme are presented. Also a brief comparison between the series AICS and the parallel AICS is included.","PeriodicalId":191010,"journal":{"name":"VIII IEEE International Power Electronics Congress, 2002. Technical Proceedings. CIEP 2002.","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117343652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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