International Workshop on System Level Interconnect Prediction最新文献

Stability and scalability in global routing 全局路由的稳定性和可扩展性

International Workshop on System Level Interconnect Prediction Pub Date : 2011-06-05 DOI: 10.1109/SLIP.2011.6135431

Sung Kyu Han, Kwangok Jeong, A. Kahng, Jingwei Lu

{"title":"Stability and scalability in global routing","authors":"Sung Kyu Han, Kwangok Jeong, A. Kahng, Jingwei Lu","doi":"10.1109/SLIP.2011.6135431","DOIUrl":"https://doi.org/10.1109/SLIP.2011.6135431","url":null,"abstract":"As the complexity of physical implementation continues to grow with technology scaling, routability has emerged as a major concern and implementation flow bottleneck. Infeasibility of routing forces a loop back to placement, netlist optimization, or even RTL design and floorplanning. Thus, to maintain convergence and a manageable number of iterations in the physical implementation flow, it is necessary to accurately predict design routability as quickly as possible. Routability estimation during placement typically exploits rough but fast global routers. Fast global routers are integrated with placers and are supposed to provide accurate congestion estimation for each iterative placement optimization, with short turn-around time. Such integrated global routers (as well as congestion estimators without global routers) should give (1) fast, and (2) stably accurate decisions as to whether a given placement is indeed routable. In this paper, we evaluate four academic global routers [14] [1] [9] [4] in terms of stability and scalability. We perturb global routing problem instances in controlled ways, and analyze the sensitivity of routing outcomes and metrics. We observe scaling suboptimality and substantial noise in most of our experiments; this suggests a future need for new global router criteria and metrics.","PeriodicalId":189723,"journal":{"name":"International Workshop on System Level Interconnect Prediction","volume":"22 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126939234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Distributed power network co-design with on-chip power supplies and decoupling capacitors 片上电源与去耦电容协同设计分布式电网

International Workshop on System Level Interconnect Prediction Pub Date : 2011-06-05 DOI: 10.1109/SLIP.2011.6135434

Selçuk Köse, E. Friedman

引用次数: 25

Architecture and performance evaluation of 3D CMOS-NEM FPGA 三维CMOS-NEM FPGA结构与性能评价

International Workshop on System Level Interconnect Prediction Pub Date : 2011-06-05 DOI: 10.1109/SLIP.2011.6135428

Chen Dong, Chen Chen, S. Mitra, Deming Chen

引用次数: 17

Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs 纳米级硅通孔对当今和未来3D集成电路设计质量的影响

International Workshop on System Level Interconnect Prediction Pub Date : 2011-06-05 DOI: 10.1109/SLIP.2011.6135435

Daehyun Kim, Suyoun Kim, S. Lim

引用次数: 25

Toward PDN resource estimation: A law of general power density 迈向PDN资源估算:一般功率密度定律

International Workshop on System Level Interconnect Prediction Pub Date : 2011-06-05 DOI: 10.1109/SLIP.2011.6135432

Kwangok Jeong, A. Kahng

引用次数: 3

Interface optimization for improved routability in chip-package-board co-design 芯片封装板协同设计中改进可达性的接口优化

International Workshop on System Level Interconnect Prediction Pub Date : 2011-06-05 DOI: 10.1109/SLIP.2011.6135430

T. Meister, J. Lienig, Gisbert Thomke

引用次数: 4

A SAT-based routing algorithm for cross-referencing biochips 基于sat的交叉比对生物芯片路由算法

International Workshop on System Level Interconnect Prediction Pub Date : 2011-06-05 DOI: 10.1109/SLIP.2011.6135436

Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang

引用次数: 9

System interconnect design exploration for embedded MPSoCs 嵌入式mpsoc系统互连设计探索

International Workshop on System Level Interconnect Prediction Pub Date : 2011-06-05 DOI: 10.1109/SLIP.2011.6135433

Chen-Ling Chou, R. Marculescu, Ümit Y. Ogras, S. Chatterjee, M. Kishinevsky, D. Loukianov

引用次数: 1

Mobile system considerations for SDRAM interface trends 移动系统对SDRAM接口趋势的考虑

International Workshop on System Level Interconnect Prediction Pub Date : 2011-06-05 DOI: 10.1109/SLIP.2011.6135437

A. Kahng, V. Srinivas

{"title":"Mobile system considerations for SDRAM interface trends","authors":"A. Kahng, V. Srinivas","doi":"10.1109/SLIP.2011.6135437","DOIUrl":"https://doi.org/10.1109/SLIP.2011.6135437","url":null,"abstract":"A variety of interconnect technologies and standards (DIMMs, MCP, POP, stacked-die and 3D-stack) enable a controller IC to communicate with an external SDRAM, or with multiple SDRAMs over a shared interconnect. Low-power requirements have driven mobile controllers to mobile-SDRAM (LPDDR) memory solutions. However, LPDDR configurations do not scale to match the throughput and capacity requirements of mobile processors, or of emerging tablet products that bring new and divergent tradeoffs among memory subsystem metrics. As a result, identifying the memory configuration best suited to a given mobile application becomes quite challenging. This paper highlights considerations in choosing a particular memory configuration for a mobile processor based on capacity, throughput, latency, power, cost and thermal concerns. We distinguish various choices according to interconnect implementation and performance, including power and timing in the IO and interconnect. To do this, we apply a three-part framework: (1) driving questions in the form of a decision tree, (2) a calculator that projects power and timing for mobile IO implementations, and (3) propagated top-down requirements and bottom-up capabilities that distinguish interconnect implementations. Our framework can support abstraction of timing and power for various interconnect configurations, to feed higher-level tools such as CACTI [19]. We anticipate that it can also be used to project mobile system requirements and memory interconnect capabilities into the future, so as to identify any gaps or bottlenecks in memory product roadmaps.","PeriodicalId":189723,"journal":{"name":"International Workshop on System Level Interconnect Prediction","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133038075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Reducing energy and increasing performance with traffic optimization in many-core systems 在多核心系统中通过流量优化降低能耗并提高性能

International Workshop on System Level Interconnect Prediction Pub Date : 2011-06-05 DOI: 10.1109/SLIP.2011.6135429

George B. P. Bezerra, S. Forrest, P. Zarkesh-Ha

引用次数: 3