Interface optimization for improved routability in chip-package-board co-design

Abstract

The simultaneous optimization of both pin assignment and pin routing for different hierarchy levels (chip, package, board) of an electronic system is a bottleneck in today's hierarchical co-design flows, typically requiring manual optimization strategies and multiple iterations. Specifically, a fast and finegrained evaluation of routability that considers all requirements between the different hierarchy levels is missing. In this paper we provide a comprehensive, fast method to evaluate the routability of interfaces in hierarchical systems based on a new probabilistic routability prediction. We implemented our methodology in an industrial design flow and achieved significant improvement in overall routing, including reduced manufacturing costs of chip-package-board co-designs.