21st Design Automation Conference Proceedings最新文献_第8页

A Gate Level Model for CMOS Combinational Logic Circuits with Application to Fault Detection CMOS组合逻辑电路的门级模型及其故障检测应用

21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585845

S. Reddy, V. Agrawal, Sunil K. Jain

引用次数: 67

Micro-Computer Oriented Algorithms for Delay Evaluation of MOS Gates 面向微机的MOS门时延评估算法

21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585819

D. Etiemble, V. Adeline, Nguyen H. Duyet, J. Ballegeer

引用次数: 8

Basic Turorial Layout Tools - What Really Is There 基本的教程布局工具-什么是真正的存在

21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585798

R. Smith

引用次数: 0

Workshop The Semi-Custom Revolution: How to Thrive or Survive 半定制革命:如何发展或生存

21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585824

A. Zingale, F. Kohn, F. Lynch, D. Kalbarsh

引用次数: 0

Test Generation for LSI: A Case Study 大规模集成电路的测试生成:案例研究

21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585793

M. Abadir, H. K. Reghbati

{"title":"Test Generation for LSI: A Case Study","authors":"M. Abadir, H. K. Reghbati","doi":"10.1109/DAC.1984.1585793","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585793","url":null,"abstract":"A new automatic test generation approach for LSI circuits has been presented in the companion papers [1] [2]. In this paper we generate tests for a typical LSI circuit using the new approach. The goal of this study is to gain insight into the problems involved in using the test generation procedures. A formal model C for a 1-bit microprocessor slice is defined which has all the main features of commercially available bit slices such as the Am2901. The circuit C is modeled as a network of interconnected functional modules. The functions of the individual modules are described using binary decision diagrams, or equivalently using experiments derived from the diagrams. Using our test generation technique, we derive tests for the circuit C capable of detecting various faults covered by our fault model [1]. It is shown that backtracking is rarely needed while generating tests for C. Also, we show that generating a multiple vector test is not required for any of the faults considered in the study. The length of the circuit's test sequence is significantly reduced using the fault collapsing method. A discussion of how to model some of the features of LSI circuits that are not included in the circuit C is presented. A comparison between the length of the test generated by our method and other manually-generated ones is also presented.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123140977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

POLARIS: Polarity Propagation Algorithm for Combinational Logic Synthesis POLARIS:组合逻辑合成的极性传播算法

21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585814

T. Shinsha, T. Kubo, M. Hikosaka, K. Akiyama, K. Ishihara

引用次数: 9

Studying the Mouse for CAD Systems CAD系统中鼠标的研究

21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585809

L. A. Price

引用次数: 3

Emerald: A Bus Style Designer Emerald:巴士风格设计师

21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585813

C. Tseng, D. Siewiorek

引用次数: 9

Module Design Verification System 模块设计验证系统

21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585808

L. Wilkins

引用次数: 0

Optimization Techniques for Two-Dimensional Placement 二维布局优化技术

21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585871

L. Markov, J. Fox, J. Blank

{"title":"Optimization Techniques for Two-Dimensional Placement","authors":"L. Markov, J. Fox, J. Blank","doi":"10.1109/DAC.1984.1585871","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585871","url":null,"abstract":"Present VLSI synthesis programs typically characterized as silicon compilers employ a predefined floorplan and fixed placement of functional elements. Significant broadening of the areas of application and more effective utilization of silicon space can be obtained by using a general placement of functionally clustered elements rather than a fixed floorplan. In this paper we present a new mathematical optimization technique to achieve a two-dimensional placement. The two-dimensional placement problem is the most important part of the hierarchical placement approach being considered by GTE Laboratories for its SilC Silicon Compiler. This paper describes a method of solving the placement problem in a mathematical form and an algorithm for optimization. The construction of a mathematical model and the use of optimization techniques represent the main distinction from heuristic placement procedures. The optimization technique guarantees a feasible placement at each iteration. It is also possible to determine at each stage how close the solution is to the optimum, and therefore the process may be stopped when the result is sufficiently close to optimum. A small, illustrative example of a two-dimensional placement problem was considered.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130544506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15