CMOS组合逻辑电路的门级模型及其故障检测应用

21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI:10.1109/DAC.1984.1585845

S. Reddy, V. Agrawal, Sunil K. Jain

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引用次数: 67

摘要

给出了CMOS组合逻辑电路门级等效电路的推导过程。这个过程导致一个包含与、或和非门的模型。具体来说，它不像早期的模型那样需要内存元素，而且使用的门也更少。结果表明，等效电路中经典卡在0和卡在1故障测试可用于检测模拟CMOS电路中的线路卡在、卡开和卡在故障。

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A Gate Level Model for CMOS Combinational Logic Circuits with Application to Fault Detection

A procedure to derive gate level equivalent circuits for CMOS combinational logic circuits is given. The procedure leads to a model containing AND, OR and NOT gates. Specifically it does not require memory elements as does an earlier model and also uses fewer gates. It is shown that tests for classical stuck-at-0 and stuck-at-1 faults in the equivalent circuit can be used to detect line stuck-at, stuck-open and stuck-on faults in the modeled CMOS circuit.

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21st Design Automation Conference Proceedings

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