发布求助
文献互助 智能选刊 最新文献

21st Design Automation Conference Proceedings最新文献

筛选
英文 中文
A Model for Hardware Description and Verification 硬件描述与验证模型
21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585803
G. Milne
{"title":"A Model for Hardware Description and Verification","authors":"G. Milne","doi":"10.1109/DAC.1984.1585803","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585803","url":null,"abstract":"Integrated circuit verification is required to establish the correctness of a circuit design before fabrication. This paper proposes CIRCAL as a model in which to describe the behaviour of devices in a natural, concise and accurate manner. CIRCAL supports a number of verification techniques which allow for the formal analysis of circuit behaviour. Properties of the model are outlined while simulation and proof techniques using CIRCAL are presented.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"38 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132375357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Functional Verification of Memory Circuits from Mask Artwork Data 基于掩模图形数据的记忆电路功能验证
21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585800
M. Kawamura, H. Takagi, K. Hirabayashi
{"title":"Functional Verification of Memory Circuits from Mask Artwork Data","authors":"M. Kawamura, H. Takagi, K. Hirabayashi","doi":"10.1109/DAC.1984.1585800","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585800","url":null,"abstract":"The timing simulator MACTIS was successfully applied to functional verification of MOS memory circuits from mask artwork data. The circuit description is extracted automatically from artwork data by the mask analysis program. Combining the macromodel technique and the code generation scheme, the timing simulation can be performed cost-effectively. MACTIS can handle circuits with analog features also, including bootstrapping effects, which cannot be done by logic and switch level simulators.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132116721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Engineering Design Aspects 工程设计方面
21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585821
Herbert Y. Chang, R. N. Talmadge
{"title":"Engineering Design Aspects","authors":"Herbert Y. Chang, R. N. Talmadge","doi":"10.1109/DAC.1984.1585821","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585821","url":null,"abstract":"EDS, a subsystem within AT&T Bell Laboratories Unified CAD system, is an integrated front-end computer-aided engineering system that is designed to facilitate the early detection and correction of design errors for system designers. This paper provides an overview of its system attributes and functional capabilities. EDS has been in wide use at AT&T Bell Laboratories and AT&T Information Systems Laboratory in support of the various hardware design activities associated with electronic switching systems, processors, transmission systems, and many other applications.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132336056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Global Routing Algorithm for General Cells 通用单元的全局路由算法
21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585771
Gary Clow
{"title":"A Global Routing Algorithm for General Cells","authors":"Gary Clow","doi":"10.1109/DAC.1984.1585771","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585771","url":null,"abstract":"An algorithm is presented which accomplishes the global routing for a building block or general cell routing problem. A line search technique is employed and therefore no grid is assumed either for the module placements or the pin locations. Instead of breaking the routing surface up into channels, a maze search finds acceptable global routes while avoiding the blocks. Both multi-pin terminals and multi-terminal nets are accomodated. It is shown that the Lee-Moore grid-based approach is actually a special case of the general search algorithm presented. This algorithm is borrowed from the field of artificial intelligence where it has been applied to many state-space search problems.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115906445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
Initial Placement of Gate Arrays Using Least-Squares Methods 用最小二乘法进行门阵列的初始布置
21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585877
J. Blanks
{"title":"Initial Placement of Gate Arrays Using Least-Squares Methods","authors":"J. Blanks","doi":"10.1109/DAC.1984.1585877","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585877","url":null,"abstract":"It is known [1] that the optimal placement of devices on a carrier is NP-complete. So algorithms are forced to rely on heuristics in order to generate placements which are of high quality even if not globally optimal.\u0000 This paper proposes the use of a metric which is the sum of the squares of the lengths of connections, for which a globally optimal assignment can be derived when overlapping components are ignored. A second placement phase maps this into a non-overlapping placement on the carrier while perturbing the derived placement as little as possible.\u0000 This is essentially the metric used in [4] although not explicitly stated. However, [4] does not deal with the problems of fixed devices, IO's and other constraints which are important to VLSI design. The current paper seeks to incorporate these constraints into the model from the beginning.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115177210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
The Rectangle Placement Language 矩形放置语言
21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585829
John Alan Roach
{"title":"The Rectangle Placement Language","authors":"John Alan Roach","doi":"10.1109/DAC.1984.1585829","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585829","url":null,"abstract":"Constraint-based symbolic layout of VLSI designs has received growing attention during the past few years. Several systems have been developed which can offer graphical or textual media for the expression of designs and can provide automatic compaction to technology specific design rules. The ability of these systems to allow for the expression of more generalized relationships is a topic open for further research. RPL is a constraint-based symbolic layout language intended to address the problem of providing a more flexible set of constraints and restraints to the designer for expressing the relationships and dependencies of the design. This paper describes some of the ideas behind this work and details some of the progress that has been made.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115873057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Block Description Language (BDL): A Structural Description Language 块描述语言(BDL):一种结构描述语言
21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.5555/800033.800777
E. Slutz, Glen K. Okita, Jeanne Wiseman
{"title":"Block Description Language (BDL): A Structural Description Language","authors":"E. Slutz, Glen K. Okita, Jeanne Wiseman","doi":"10.5555/800033.800777","DOIUrl":"https://doi.org/10.5555/800033.800777","url":null,"abstract":"The Block Description Language (BDL), a language for capturing the structure of an electronic system, is described. The structure of a system may be specified hierarchically in this language. Additional information may be associated with the structural description with general properties. A facility for declaring and using arrays and records of the structure elements is provided.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125407052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A General Methodology for Synthesis and Verification of Register-Transfer Designs 寄存器转移设计的综合与验证的一般方法
21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585815
A. C. Parker, F. Kurdahi, M. Mlinar
{"title":"A General Methodology for Synthesis and Verification of Register-Transfer Designs","authors":"A. C. Parker, F. Kurdahi, M. Mlinar","doi":"10.1109/DAC.1984.1585815","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585815","url":null,"abstract":"The general relationship between register-transfer synthesis and verification is discussed, and common mechanisms are shown to underlie both tasks. The paper proposes a framework for combined synthesis and verification of hardware that supports any combination of user-selectable synthesis techniques. The synthesis process can begin with any degree of completion of a partial design, and verification of the partial design can be achieved by completing its synthesis while subjecting it to constraints that can be generated from a \"template\" and user constraints. The driving force was the work done by Hafer [3] on a synthesis model. The model was augmented by adding variables and constraints in order to verify interconnections. A multilevel, multidimensional design representation [6] is introduced which is shown to to be equivalent to Hafer's model. This equivalence relationship is exploited in deriving constraints off the design representation. These constraints can be manipulated in a variety of ways before being input to a linear program which completes the synthesis/verification process. An example is presented in which verification and synthesis occur simultaneously and the contribution of each automatically varies, depending on the number of previous design decisions.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126659684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
An Integrated Design for Testability and Automatic Test Pattern Generation System: An Overview 可测试性与自动测试模式生成系统的集成设计综述
21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.1109/DAC.1984.1585796
E. Trischler
{"title":"An Integrated Design for Testability and Automatic Test Pattern Generation System: An Overview","authors":"E. Trischler","doi":"10.1109/DAC.1984.1585796","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585796","url":null,"abstract":"A general overview on an Integrated Design for Testability and Automatic Test Pattern Generation System (IDAS) is given. The major components of IDAS include: heuristic controllability/observability (C/O) analysis, prediction of testing costs, tools for evaluation, display and improvement of testability, and C/O guided automatic test pattern generator. The IDAS system includes also the logic and concurrent fault simulator CADAT. A brief description of major components with a scenario how to use IDAS is given. Future research activities are discussed.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127059303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Formal Design Verification System Based on an Automated Reasoning System 基于自动推理系统的形式化设计验证系统
21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI: 10.5555/800033.800867
A. S. Wojcik, J. Kljaich, N. Srinivas
{"title":"A Formal Design Verification System Based on an Automated Reasoning System","authors":"A. S. Wojcik, J. Kljaich, N. Srinivas","doi":"10.5555/800033.800867","DOIUrl":"https://doi.org/10.5555/800033.800867","url":null,"abstract":"In recent years, interest has grown in the possibility of developing a formal design verification approach as an alternative to standard simulation techniques for verification. Several researchers have used, or suggested the use of, artificial intelligence techniques in such a formal system. The purpose of this paper is to briefly describe the ongoing work on the development of a viable formal design verification system based on an automated reasoning system. This system, called LMA (Logic Machine Architecture), has been developed at Argonne National Laboratory. This paper describes the basic ideas underlying this formal system for verification and discusses several of the current research projects.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126086810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信