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2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)最新文献

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A Coarse-Fine Dual Loop Digital Low Dropout Regulator with Fast Transient Response 一种快速瞬态响应的粗精双环数字低差稳压器
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754116
Jiangyi Shi, Bo Zhao, Bowen Wang
{"title":"A Coarse-Fine Dual Loop Digital Low Dropout Regulator with Fast Transient Response","authors":"Jiangyi Shi, Bo Zhao, Bowen Wang","doi":"10.1109/EDSSC.2019.8754116","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754116","url":null,"abstract":"A coarse-fine dual loop digital LDO with fast transient response is proposed in this paper. The proposed digital LDO incorporates both undershoot detector and gate-bulk dual modulation technology to reduce the output voltage’ undershoot. In order to improve process scalability, the controller of the digital LDO only employs digital standard cells, in which the dynamic comparator is replaced by a synthesizable digital comparator. The digital LDO is simulated in a 65nm CMOS process. A 0.5V stable output voltage and a 20mA output current is achieved with a 0.6V input voltage. A maximum voltage undershoot of 90mv is simulated with a 15mA load step and a total capacitor of 130pF.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"28 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114014765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Influence of energy band of n+ a-Si thin films on performance of IBC-SHJ solar cells n+ a-Si薄膜能带对IBC-SHJ太阳能电池性能的影响
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754130
Jianhui Bao, K. Tao, R. Jia, Aimin Liu
{"title":"Influence of energy band of n+ a-Si thin films on performance of IBC-SHJ solar cells","authors":"Jianhui Bao, K. Tao, R. Jia, Aimin Liu","doi":"10.1109/EDSSC.2019.8754130","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754130","url":null,"abstract":"Interdigitated back contact silicon heterojunction (IBC-SHJ) solar cells exhibit excellent performance because of the combination of IBC structure and SHJ technology. The front surface field (FSF) which consists of chemical passivated layer and electrical field passivated layer, has proved to be very important for achieving high conversion efficiency. In term of electrical field passivated layer, the n+doped thin films based on alloys of Si with carbon or oxygen in amorphous phases (n+a-Si) is present by Sentaurus TCAD to investigate energy band performance. The simulation result indicates that the n+a-Si layer with wider energy band reduces the light absorption on the front surface effectively, results in large improvement in short circuit current density (Jsc). As field passivated layer, the wider energy band of n+ a-Si leads no effect on better passivation. The main role creating electrical field is doping concentration, and field passivation effect enhance as doping concentration increasing. With the better optical performance and field passivation, the conversion efficiency achieve above 26% on the poor interfacial chemical passivation using wider n+a-Si layer on the front surface.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126361174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A High Speed Extension Field Multiplier for Pairing Acceleration 用于配对加速的高速扩展场乘法器
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8753928
Guantong Su, Xingjun Wu, Guoqiang Bai
{"title":"A High Speed Extension Field Multiplier for Pairing Acceleration","authors":"Guantong Su, Xingjun Wu, Guoqiang Bai","doi":"10.1109/EDSSC.2019.8753928","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753928","url":null,"abstract":"In this paper, we present a high performance extension field multiplier for pairing acceleration on reconfigurable device. It is shown that combining Residue Number System (RNS), which is designed for concurrent architecture and modern FPGA programmable logic array. The parallelism of RNS can be fully exploited. The proof of concept is implemented on a Xilinx Ultrascale $+FPGA$, which takes 352 DSPs and accomplish a $F_{p^{6}}$ multiplication in 44 cycles at a $500MHz$ clock frequency.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121450408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Towards Low Space Complexity Design of Gaussian Normal Basis Multiplication 高斯正态基乘法的低空间复杂度设计
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754096
Xuemei Tian, X. Wu, Guoqiang Bai
{"title":"Towards Low Space Complexity Design of Gaussian Normal Basis Multiplication","authors":"Xuemei Tian, X. Wu, Guoqiang Bai","doi":"10.1109/EDSSC.2019.8754096","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754096","url":null,"abstract":"Normal basis is hardware-friendly to perform squaring operations over binary fields. It is very attractive in some applications, like elliptic curve cryptography over Koblitz curves. In this paper, a new algorithm is proposed to reduce the space complexity of Gaussian Normal Basis (GNB) multiplier over GF$(2^{163})$ and GF$(2^{40}9)$. As far as we know, by applying this method, the number of XOR gates needed for a bit-level SIPO GNB multiplier over GF$(2^{163})$ and GF$(2^{409})$ can be minimized. Also, it is a general methodology suitable for all binary fields that involve type -4 Gaussian Normal Basis.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132069910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Digital Neuromorphic Hardware for Spiking Neural Network 一种用于脉冲神经网络的数字神经形态硬件
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754093
Yuanning Fan, Chenglong Zou, Kefei Liu, Yisong Kuang, Xiaoxin Cui
{"title":"A Digital Neuromorphic Hardware for Spiking Neural Network","authors":"Yuanning Fan, Chenglong Zou, Kefei Liu, Yisong Kuang, Xiaoxin Cui","doi":"10.1109/EDSSC.2019.8754093","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754093","url":null,"abstract":"The neuromorphic hardware with a non-von Neumann architecture has the advantage of highly-parallel and low-power. In this paper, a digital neuromorphic core with 1024 neurons, 1024 axons and a $1024times 1024$ synaptic crossbar is designed, and the scalable network could be implemented based on the 2D mesh network on chip (NOC) architecture. The transformed deep spiking neural network (SNN) models can be mapped to our hardware directly, and show good application results. At the case of the full firing rate, the average power of a spike is 2.76E-08J, and for some image recognition tasks, the hardware power consumption is at the milliwatt level.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133914220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Compact and Compound SCR structure for full chip ESD protection 紧凑和复合可控硅结构，全芯片ESD保护
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754315
Xiaoyu Dong, Feibo Du, Fei Hou, Wenqiang Song, Zhiwei Liu, Jizhi Liu
{"title":"Compact and Compound SCR structure for full chip ESD protection","authors":"Xiaoyu Dong, Feibo Du, Fei Hou, Wenqiang Song, Zhiwei Liu, Jizhi Liu","doi":"10.1109/EDSSC.2019.8754315","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754315","url":null,"abstract":"Traditional full chip electrostatic discharge (ESD) protection circuits consumes a large amount of chip area. To resolve this problem, a novel three-terminal compact and compound SCR (CCSCR) is proposed. The proposed CCSCR employs intrinsic parasitic SCRs and ESD diodes as main ESD discharge paths to independently implement full chip ESD protection, which can greatly reduce area consumption and achieve high ESD robustness. The TCAD simulation indicates that the proposed CCSCR has a low trigger voltage and a high holding voltage. In addition, RC detection circuit is also introduced into CCSCR to further reduce the trigger voltage and improve the holding voltage, which makes CCSCR more efficient as a candidate ESD device in nanoscale CMOS technology.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129404006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Snapback-Free Reverse-Conducting IGBT with Integrated Schottky Diode in the Collector 集电极中集成肖特基二极管的无snapback反导IGBT
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8753994
Jin-ping Zhang, Junyi Luo, Kang L. Wang, Yang Zhao, Zehong Li, M. Ren, Wei Gao, Bo Zhang
{"title":"A Snapback-Free Reverse-Conducting IGBT with Integrated Schottky Diode in the Collector","authors":"Jin-ping Zhang, Junyi Luo, Kang L. Wang, Yang Zhao, Zehong Li, M. Ren, Wei Gao, Bo Zhang","doi":"10.1109/EDSSC.2019.8753994","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753994","url":null,"abstract":"A novel snapback-free reverse-conducting insulated gate bipolar transistor with integrated schottky diode in the collector (ISD-RC-IGBT) is proposed. The proposed structure features an ISD between the n+collector and the n field stop (FS) layer in the device bottom. The simulation results show that compared to the conventional RC-IGBT, the proposed device demonstrates excellent overall performance in both IGBT and diode modes. Meanwhile, the device reliability is also improved owing to the uniform carriers and current distribution in the drift region in both IGBT and diode modes.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132812887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Stealthy Trojan Detection Based on Feature Analysis of Circuit Structure 基于电路结构特征分析的木马隐身检测
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754248
Jiatong Tan, Jianhua Feng, Yinxuan Lyu
{"title":"Stealthy Trojan Detection Based on Feature Analysis of Circuit Structure","authors":"Jiatong Tan, Jianhua Feng, Yinxuan Lyu","doi":"10.1109/EDSSC.2019.8754248","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754248","url":null,"abstract":"The design methods and the detection methods for Hardware Trojan develop rapidly. Existing trustiness verification methods are effective to obviously malicious HT but no effect on Stealthy Trojan. Stealthy Trojan is an advanced attack form and hard to be detected. In this paper, we analyze the characteristic of stealthy Trojan and propose a static detection method based on feature analysis. The results on ISCAS benchmarks show that the proposed method can detect the Stealthy Trojan node and is convenient to be implanted into other scalable verification framework.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115614567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Adaptive Single Event Upset (SEU)-Hardened Flip-Flop Design 一种自适应单事件干扰(SEU)硬化触发器设计
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754303
Man Zhang, Zhongjie Guo, Wancheng Xu
{"title":"An Adaptive Single Event Upset (SEU)-Hardened Flip-Flop Design","authors":"Man Zhang, Zhongjie Guo, Wancheng Xu","doi":"10.1109/EDSSC.2019.8754303","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754303","url":null,"abstract":"In this paper, a new radiation hardened flip-flop design technique is proposed. The structure provides an possibility that the D-type flip-flop can be configured as an Single Event Upset (SEU) hardened or non-hardened flip-flop in a circuit based on the logic states of the sensitive nodes with RC filtering structure being involved or not, considering speed and reliability. The proposed structure makes itself more widely used in both space, defense applications and high-performance terrestrial applications. Spice simulation results show that the flip-flop has good performance of SEU-hardness and flexibility.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"363 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115976620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of a high precision delay locked loop for the readout chip of cosmic ray muon detector 宇宙射线介子探测器读出芯片高精度延时锁环设计
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754008
Jianfu Liu, T. Wei, Nan Chen, Xiaochun He
{"title":"Design of a high precision delay locked loop for the readout chip of cosmic ray muon detector","authors":"Jianfu Liu, T. Wei, Nan Chen, Xiaochun He","doi":"10.1109/EDSSC.2019.8754008","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754008","url":null,"abstract":"A high precision delay locked loop (DLL) is designed for the readout circuit chip of a multi-channel cosmic ray muon detector in this paper. In order to decrease the system clock frequency and increase the measurement accuracy of muon signal, the DLL-based readout circuit architecture is preferred. The designed DLL has the features of wide dynamic clock range, high stability and high precision, which is implemented by a TSMC 0.18 μm mixed-signal CMOS process. The simulation results show that, the locking time of the DLL is 7 us, the locked frequency range is 30~60 MHz, and the statistical error of jitter is less than 150 ps. The performances of designed DLL are satisfied with the requirements of the readout circuit chip for a multi-channel cosmic ray muon detector.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124304120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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