International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.最新文献

{"title":"A parallel view maintenance algorithm for complete consistency","authors":"S. A. Fouad, O. Karam, M. El-Sharkawy","doi":"10.1109/ICEEC.2004.1374403","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374403","url":null,"abstract":"In recent years, numerous algorithms have been proposed for View Maintenance of Data Warehouses (DWs). Most of these algorithms concentrate on maintaining a complete level of consistency. Transactions containing concurrent updates with parallel View Maintenance complicate the consistency problem. The PVM-MED WRAP algorithm is an efficient parallel DW View Maintenance algorithm that manipulates concurrent updates in a distributed multi-relation sources environment. However, this algorithm only ensures the Convergence level of consistency. This paper extends the PVM-MED WRAP algorithm to achieve the Complete level of consistency, and presents a scalable architecture for the proposed algorithm Simulation results demonstrate that extending the P VMMEDWRAP algorithm to achieve the Complete level of consistency limits the maximal parallelism feature, and hence decreases the performance improvement of the system. But this is the price in terms ofperformance in order to achieve fhe Complete level of consistency.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122842268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A lossless H.263 video codec using the reversible DCT","authors":"S. Gharbi, M. El-Sharkawy, P. Salama, M. Rizkalla","doi":"10.1109/ICEEC.2004.1374481","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374481","url":null,"abstract":"Unified lossless and lossy image coding system is useful for various applications, since we can reconstruct lossy and lossless images from a part and the whole of the encoded data, respectively. This coding system can be realized by using reversible transforms. Reversible wavelet transform (R WT), Lossless-DCT (LDCT) and reversible Walsh-Hadamard transform (R WHT) have been proposed as reversible transforms. In this paper, an N-point reversible discrete cosine transform (RDCT) based H.263 video codec is presented, then 8-point RDCT is obtained by substituting the 2 and 4-point reversible transforms for 2 and 4-point transforms which compose 8-point discrete cosine transform (DCT), respectively. Integer input signal can be losslessly recovered, although the transform coefficients are integer numbers. The RDCT is then implemented on the H.263 video codec. Simulations of the RDCT-based H.263 shows a petfect reconstruction of the original video sequence in lossless mode, and lossy compression efJiciencies comparable to those obtained with the conventional fast DCT-based H.263 in low bit rates. where L.1 corresponds to downward truncation, 80 and el are integer transform coefficients and ~0 and X I are integer inputs. If the real numbers CO and C I satisfy CO C I 5 0, this transform becomes reversible. If the floor functions are deleted, the determinant of the transform matrix becomes (1 CO cl). Therefore redundancy occurs in transform domain, when co cI < 0. This problem is avoided by using the following transform instead: It is obvious that this transform is reversible for any co and c1. If the floor functions are deleted, the coefficients of xo and X I of 81 become cI and ( I+ CO cl), respectively, that is, the determinant becomes 1. However, the problem that the dynamic range is nonuniform remains. The dynamic range can become uniform by using the following transform instead: I. THE REVERSIBLE DISCRETE COSINE TRANSFORM: RDCT In this section, a reversible discrete cosine transform (RDCT) is presented. When integer input signal is transformed by DCT, the transform Eoefficients become real. Therefore the quantization step must be reduced in order to reconstruct input losslessly. This results in low compession efficiency. where the transform coefficients are and Oz. a) 2-Point Reversible Transform: Let's consider the following 2-point transform: 0-7803-8575-6/04/$20.00 02004 IEEE 407 Figure 1 : 2-Point Reversible Transform Ladder Network. (3) Figure 1 shows the ladder network for the 2-point reversible transform, where quantizer, R, represents rounding to the nearest integer, xi are integer inputs, 0i are integer outputs and ci are real multipliers. If the floor functions are deleted, the coefficients of xo and XI of 81 become cl and (1+ CO cl), respectively, and those of 02 become (1+ C I CZ) and (CO+ c2f CO C I c2), respectively, Therefore, the determinant becomes 1 : [:]=[I CO +c, +CoCqC, I [ : ; ] (4) The inverse transform is as follows : b) N-Poi","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124793007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multilevel optimization control for large-scale systems using genetic algorithms","authors":"E.E. EL Mdbouly, A. Ibrahim, G. Z. El-Far, M. El Nassef","doi":"10.1109/ICEEC.2004.1374419","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374419","url":null,"abstract":"This paper presents a modijied approach to design multilevel controllers using structural perturbation technique for large-scale systems based on genetic algorithms. The powerful capabilities of genetic algorithms in locating the optimal solution to a given optimization problem are exploited to determine the parameters of the controller in order to meet specijied performance objectives. The proposed approach is based on obtaining local feedback controller for each subsystem in the first level by ignoring the interaction, and then a global controller at the second level provides corrective signals to neutralize the interaction effects. The proposed control approach is used successfully to control the behaviour of a two-area power system. Simulation results are presented to illustrate the effectiveness of the proposed control approach compared to traditional method Index Terms Genetic algorithm, Large-scale systems, Optimization, Multilevel control","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124851527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wind energy system voltage and energy enhancement using low cost dynamic capacitor compensatio scheme","authors":"A. Sharaf, Guosheng Wang","doi":"10.1109/ICEEC.2004.1374601","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374601","url":null,"abstract":"Abstract The paper presents a novel low cost dynamic capacitor compensation scheme using real time dynamic error tracking and harmonic ripple based PID controller to stabilize an isolated stand alone Wind Energy Conversion Scheme (WECS) with a induction generator. The novel Dynamic Capacitor Compensation scheme (DCC) serves as a voltage stabilization regulator and energy utilization enhancement compensator.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125040099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The characteristic mode theory of the filed penetration into a cylindrical waveguide through rectangular aperture, TM case","authors":"K. Kabalan, A. El-Hajj, F. Elias","doi":"10.1109/ICEEC.2004.1374539","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374539","url":null,"abstract":"The problem of aperture in conducting media has been widely considered in the literature. This problem addresses the case of an electromagnetic wave incident on a structure of conducting material segmenting space into two or more regions coupled through one or more aperture in the walls of the conductor. The purpose would be to compute the electromagnetic field everywhere in space due to the incident wave. The method of characteristic modes has been successfully used to solve this problem for several configurations for the conducting structure and aperture shape. This paper uses this method to solve the aperture problem for a cylindrical conducting guide coupled to open half space through a rectangular aperture. The theory offiled computation at both sides of the apertures are determined as a function of the aperture and cylinder dimensions.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123292471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On the design flow of a hardware/software platform for MPEG-4 part 9 reference hardware model","authors":"T. Mohamed, M. Sayed, Wael Badawy","doi":"10.1109/ICEEC.2004.1374479","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374479","url":null,"abstract":"This paper illustrates the design and implementation of an integrated hardware-software platform for image processing. This platform is versatile as it is configurable at run time. This platform is configured to act as a co-processor for the main processor of a host personal computer such that a complex computational task is moved to hardware and the processing on part of the host computer is reduced to just data communication with the co-processor. Thus, the proposed solution makes complex multimedia processing tasks feasible on handheld devices with low processing power and limited battery life. The concept is illustrated by a prototype system for image compression. The hardware part is an FPGA board that can be plugged into a standard PCMCIA socket on any portable system. The FPGA is configured at run time to perform the two most computationally extensive tasks in MPEG-4; namely; motion estimation and discrete cosine transform. The complete hardware/software prototype was integrated as a part of MPEG-4 encoder software. The measured results indicate that the overall system speed is independent of the speed of the processor of the host computer. The hardware part design is based on systolic architectures and satisfzes better than real time performance with low power consumption. Index Terms Hardware/software integration, Multimedia, MPEG-4, Discrete cosine transform, Motion Estimation.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129790548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"JPEG 2000 performance evaluation","authors":"M.E. Allam, E. Abdel-Ghaffar","doi":"10.1109/ICEEC.2004.1374477","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374477","url":null,"abstract":"AbsfructThis paper compares the set of features offered by JPEG 2000, the new IS0 / ITU-T standard for still image coding and the popular JPEG. The study concentrates on functionality set, while addressing other aspects such as Region of Interest coding (ROI), superior low bit rate performance, and memory requirements. Also, compressed image quality is evaluated using various algorithms. The principles behind each algorithm are brie?y described. The results show that the JPEG 2000 supports a wide set of features that JPEG can either not address eflciently or not address at all.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129203908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Validation of RF mosfet transistor layout-aware macromodel","authors":"A. El-Sabban, H. Haddara, H. Ragai","doi":"10.1109/ICEEC.2004.1374519","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374519","url":null,"abstract":"In this paper, an overview of a layout-aware macromodel for the BSIM3v3 MOSFET transistor in RF applications is presented. This layout-aware macromodel includes all the terminal access series resistences including substrate as well as the junction capacitances. It can be used for circuit simulation at RF up to 6GHz. The model is validated for a 0. 3 5 ~ CMOS process using a transistor with total width of 9 0 p and 18 fingers. The simulation results show an excellent agreement with the fi and S-parameter measurement data. The layout-aware macromodel presented in this paper can be easily modified to account for various layout transistor structures and technology parameters depending on the required application.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"28 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127562387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Designing fault-tolerant meshes and hypercubes using circulant graphs","authors":"S. Lou, A. Farrag","doi":"10.1109/ICEEC.2004.1374442","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374442","url":null,"abstract":"Many important architectures such as rings, meshes and hypercubes can be modeled as circulant graphs. As a result, circulant graphs have received a lot of attention, and a new method was developed for designing fault-tolerant solutions for them. We review this method in this paper, and examine its applications to the design of fault-tolerant solutions for meshes and hypercubes. Our results indicate that the solutions obtained are eficient.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121089956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A modification of RC6/sup tm/ block cipher algorithm for data security (MRC6)","authors":"N. El-Fishawy, T.E. El-Danaf, O.M. Abou Zaid","doi":"10.1109/ICEEC.2004.1374428","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374428","url":null,"abstract":"In this paper, a modijkation of RC6 block cipher (MRC6) is introduced. MRC6 is a symmetric encryption algorithm designed to meet the requirements of the Advanced Encryption Standard (AES). It is an enhanced extension of RC6 with improving performance. It makes essential heavy use of data-dependent rotations. Its features include using of sixteen (I@-working registers instead of four registers in RC6. Using the integer multiplication with sixteen working registers greatly increases the diSfusion achieved per round, and allows for greater security with fewer rounds. It is also capable to handle 512-bit plaintext and ciphertext block sizes with decreasing in encryptioddecryption time and increasing in throughput. Comparative performance evaluation of MRC6 with ERC6, RC6, and RC5 is introduced. Simulation results show that MRC6 achieves minimum encryptioddecryption time and maximum throughput. So, the proposed modijication is expected to satis& market demands and system security developers using advanced processors available.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132127997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}