On the design flow of a hardware/software platform for MPEG-4 part 9 reference hardware model

This paper illustrates the design and implementation of an integrated hardware-software platform for image processing. This platform is versatile as it is configurable at run time. This platform is configured to act as a co-processor for the main processor of a host personal computer such that a complex computational task is moved to hardware and the processing on part of the host computer is reduced to just data communication with the co-processor. Thus, the proposed solution makes complex multimedia processing tasks feasible on handheld devices with low processing power and limited battery life. The concept is illustrated by a prototype system for image compression. The hardware part is an FPGA board that can be plugged into a standard PCMCIA socket on any portable system. The FPGA is configured at run time to perform the two most computationally extensive tasks in MPEG-4; namely; motion estimation and discrete cosine transform. The complete hardware/software prototype was integrated as a part of MPEG-4 encoder software. The measured results indicate that the overall system speed is independent of the speed of the processor of the host computer. The hardware part design is based on systolic architectures and satisfzes better than real time performance with low power consumption. Index Terms Hardware/software integration, Multimedia, MPEG-4, Discrete cosine transform, Motion Estimation.