Validation of RF mosfet transistor layout-aware macromodel

Abstract

In this paper, an overview of a layout-aware macromodel for the BSIM3v3 MOSFET transistor in RF applications is presented. This layout-aware macromodel includes all the terminal access series resistences including substrate as well as the junction capacitances. It can be used for circuit simulation at RF up to 6GHz. The model is validated for a 0. 3 5 ~ CMOS process using a transistor with total width of 9 0 p and 18 fingers. The simulation results show an excellent agreement with the fi and S-parameter measurement data. The layout-aware macromodel presented in this paper can be easily modified to account for various layout transistor structures and technology parameters depending on the required application.