Proceedings International Parallel and Distributed Processing Symposium最新文献_第3页

Stable checkpointing in distributed systems without shared disks 无共享磁盘的分布式系统中的稳定检查点

Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213392

P. Sobe

引用次数: 18

Applying aspect-orient programming concepts to a component-based programming model 将面向方面的编程概念应用于基于组件的编程模型

Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213376

T. Eidson, J. Dongarra, V. Eijkhout

{"title":"Applying aspect-orient programming concepts to a component-based programming model","authors":"T. Eidson, J. Dongarra, V. Eijkhout","doi":"10.1109/IPDPS.2003.1213376","DOIUrl":"https://doi.org/10.1109/IPDPS.2003.1213376","url":null,"abstract":"The execution environments for scientific applications have evolved significantly over the years. Vector and parallel architectures have provided significantly faster computations. Cluster computers have reduced the cost of high-performance architectures. However, the software development environments have not keep pace. Object-oriented and component-based languages have not been widely adopted. Distributed computing on local area networks and Grids is only being used by a most number of applications. Clearly, there is a need for development environments that support the efficient creation of applications that use modern execution systems. This has been the goal of a continuing research effort over the last several years. The previous focus has been on using component-based ideas to develop a programming model and associated framework to support such a development approach. In this paper, two additional concepts are added to the base approach. Aspect-oriented concepts are applied to support the reduction of intertwined code related to different programming concerns; mixing I/O with a numerical computation is one example. Particularly in large applications, intertwining code can lead to applications that are difficult to modify and to manage. The second concept being added is the use of behavioral metadata. When coupling smaller pieces of code (or components) to make a larger composite application, one needs to determine the suitability of the internal behavior of component as well as the compatibility of its interfaces. The objective is to integrate some of this information into the component and design a framework assist the programmer in making these decisions.","PeriodicalId":177848,"journal":{"name":"Proceedings International Parallel and Distributed Processing Symposium","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130667424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

A Hierarchical sparse matrix storage format for vector processors 向量处理器的分层稀疏矩阵存储格式

Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213156

Pyrrhos Stathis, S. Vassiliadis, S. Cotofana

{"title":"A Hierarchical sparse matrix storage format for vector processors","authors":"Pyrrhos Stathis, S. Vassiliadis, S. Cotofana","doi":"10.1109/IPDPS.2003.1213156","DOIUrl":"https://doi.org/10.1109/IPDPS.2003.1213156","url":null,"abstract":"We describe and evaluate a Hierarchical Sparse Matrix (HiSM) storage format designed to be a unified format for sparse matrix applications on vector processors. The advantages that the format offers are low storage requirements, a flexible structure for element manipulations and allowing for efficient operations. To take full advantage of the format we also propose a vector architecture extension that supports the HiSM format. We show that utilizing the HiSM format we can achieve 40% reduction of storage space when comparing to the compressed row storage (CRS) and jagged diagonal (JD) storage methods. Utilizing the HiSM storage on a vector processor we can significantly increase the vector performance for sparse matrix vector multiplication (SMVM) by 5.3 times compared to CRS and 4.07 times compared to JD. Finally, to illustrate the flexibility of the format we compared the cost of an element insertion against the JD and CRS formats. We show that for an element insertion operation HiSM outperforms JD for average and large matrices although it has a slight disadvantage for small matrices and always outperforms CRS between 2 and 400 times.","PeriodicalId":177848,"journal":{"name":"Proceedings International Parallel and Distributed Processing Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123189851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Implementing a scalable ASC processor 实现可伸缩的ASC处理器

Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213482

Hong Wang, R. Walker

引用次数: 18

Design and evaluation of a parallel HOP clustering algorithm for cosmological simulation 一种用于宇宙模拟的并行HOP聚类算法的设计与评价

Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213186

Y. Liu, W. Liao, A. Choudhary

引用次数: 22

Automated RTR temporal partitioning for reconfigurable embedded real-time system design 用于可重构嵌入式实时系统设计的自动RTR时间分区

Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213328

C. Tanougast, Y. Berviller, Philippe Brunet, S. Weber

引用次数: 3

A multiple segmented backups scheme for dependable real-time communication in multihop networks 多跳网络中可靠实时通信的多分段备份方案

Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213240

G. Ranjith, C. Murthy

{"title":"A multiple segmented backups scheme for dependable real-time communication in multihop networks","authors":"G. Ranjith, C. Murthy","doi":"10.1109/IPDPS.2003.1213240","DOIUrl":"https://doi.org/10.1109/IPDPS.2003.1213240","url":null,"abstract":"Several distributed real-time applications require fault-tolerance apart from guaranteed timeliness at acceptable levels of overhead. It is essential to provide them with hard guarantees on recovery delays due to component-failures, which cannot be ensured in traditional datagram services. The application of computer networks have expanded to areas in which communication services are considered critical and the failure of which may lead to mission threatening scenarios. These critical communication services need to survive multiple, simultaneous component faults that can occur in the network, due to various reasons. Several schemes exist which attempt to guarantee recovery in a timely and resource efficient manner from such multiple faults. These methods center around apriori reservation of network resources called spare resources along backup channels, in addition to each primary channel. These backup channels (end-to-end backup) are usually routed from the source to the destination along a path disjoint with the primary. If a primary channel fails, one of the backups can be activated, and this makes the realtime connection dependable. In this paper, we propose a new method of multiple segmented backups for dependable communication in multihop networks, which improves upon existing methods. Various scenarios in multihop networks (including the current Internet) where our scheme can be implemented are also discussed. Finally, we demonstrate the superiority of our method by presentation of the results of our simulation studies.","PeriodicalId":177848,"journal":{"name":"Proceedings International Parallel and Distributed Processing Symposium","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121669139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Metrics for reconfigurable architectures characterization: remanence and scalability 可重构架构特征的度量:剩余性和可伸缩性

Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213324

P. Benoit, G. Sassatelli, L. Torres, D. Demigny, M. Robert, G. Cambon

{"title":"Metrics for reconfigurable architectures characterization: remanence and scalability","authors":"P. Benoit, G. Sassatelli, L. Torres, D. Demigny, M. Robert, G. Cambon","doi":"10.1109/IPDPS.2003.1213324","DOIUrl":"https://doi.org/10.1109/IPDPS.2003.1213324","url":null,"abstract":"Target applications for mobile devices such as PDA and cellular telephones require increasingly powerful architectures. This challenge has spawned different hardware acceleration styles like configurable instruction set processors, coprocessors, and ASIC. Despite acceptable, these solutions show today a lack of flexibility considering rapidly changing standards. Structurally programmable architectures can today provide a trade-off between performance of hardwired logic and flexibility of processors. More and more reconfigurable architectures are today available as IP cores for SoC designers. These ones often differ according to several parameters (granularity, reconfiguration mode, topology...). Therefore, it is not straightforward to compare different architectures and choose the right one considering both actual and future requirements. This paper proposes a general model for reconfigurable architectures and gives a set of metrics which prove useful for architecture characterization. The methodology is illustrated on a dynamically reconfigurable architecture: the systolic ring.","PeriodicalId":177848,"journal":{"name":"Proceedings International Parallel and Distributed Processing Symposium","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124148044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Sequence alignment on the Cray MTA-2 克雷MTA-2的序列比对

Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213285

S. Bokhari, J. Sauer

引用次数: 13

Optimized one-to-one personalization of Web applications using a graph based model 使用基于图的模型优化了Web应用程序的一对一个性化

Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213445

G. Sonneck, Thomas A. Mück

引用次数: 1