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Performance and overhead in a hybrid reconfigurable computer 混合可重构计算机的性能和开销
Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213325
Osman Devrim Fidanci, D. Poznanovic, K. Gaj, T. El-Ghazawi, N. Alexandridis
{"title":"Performance and overhead in a hybrid reconfigurable computer","authors":"Osman Devrim Fidanci, D. Poznanovic, K. Gaj, T. El-Ghazawi, N. Alexandridis","doi":"10.1109/IPDPS.2003.1213325","DOIUrl":"https://doi.org/10.1109/IPDPS.2003.1213325","url":null,"abstract":"In this paper, we overview general hardware architecture and programming model of SRC-6E/spl trade/ reconfigurable computers, and compare the performance of the SRC-6E machine with the Intel/spl reg/ Pentium IV/spl trade/. SRC-6E execution time measurements have been performed using three different approaches. In the first approach, the entire end-to-end execution time is taken into account. In the second approach, the configuration time of FPGA have been omitted. In the third approach both configuration and data transfer overheads have been omitted. All measurements have been done for different numbers of data blocks. The results show that the SRC-6E can outperform a general-purpose microprocessor for computationally intensive algorithms by a factor of over 1500. However, overhead due to configuration and data transfer must be properly dealt with by the application or the system's run-time environment to achieve the full throughput potential. Some techniques are suggested to minimize the influence of the configuration time and maximize the overall end-to-end system performance.","PeriodicalId":177848,"journal":{"name":"Proceedings International Parallel and Distributed Processing Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115229058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Protein structure prediction by applying an evolutionary algorithm 基于进化算法的蛋白质结构预测
Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213291
R. O. Day, G. Lamont, R. Pachter
{"title":"Protein structure prediction by applying an evolutionary algorithm","authors":"R. O. Day, G. Lamont, R. Pachter","doi":"10.1109/IPDPS.2003.1213291","DOIUrl":"https://doi.org/10.1109/IPDPS.2003.1213291","url":null,"abstract":"Interest in protein structure prediction is widespread, and has been previously addressed using evolutionary algorithms, such as the simple genetic algorithm (GA), messy GA (mga), fast messy GA (fmGA), and linkage learning GA (LLGA). However, past research used off the shelf software such as GENOCOP, GENESIS, and mGA. In this study we report results of a modified fmGA, which is found to be \"good\" at finding semi-optimal solutions in a reasonable time. Our study focuses on tuning this fmGA in an attempt to improve the effectiveness and efficiency of the algorithm in solving a protein structure and in finding better ways to identify secondary structures. Problem definition, protein model representation, mapping to algorithm domain, tool selection modifications and conducted experiments are discussed.","PeriodicalId":177848,"journal":{"name":"Proceedings International Parallel and Distributed Processing Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115434300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Sparse WDM optical interconnects under wavelength-based model 基于波长模型的稀疏WDM光互连
Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213110
Yuanyuan Yang, Jianchao Wang
{"title":"Sparse WDM optical interconnects under wavelength-based model","authors":"Yuanyuan Yang, Jianchao Wang","doi":"10.1109/IPDPS.2003.1213110","DOIUrl":"https://doi.org/10.1109/IPDPS.2003.1213110","url":null,"abstract":"Optical communication, in particular, wavelength division multiplexing (WDM) technique, has become a promising networking choice to meet ever-increasing demands on bandwidth from emerging bandwidth-intensive computing/communication applications. As optics become a major networking media in all communications needs, optical interconnects will inevitably play an important role in interconnecting processors in parallel and distributed computing systems. In this paper, we consider cost-effective designs of WDM optical interconnects for current and future generation parallel and distributed computing and communication systems. We first classify WDM optical interconnects into two different connection models based on their target applications: the wavelength-based model and the fiber-link-based model. We then focus on the wavelength-based model and present a minimum cost design for WDM optical interconnects by using sparse crossbar switches instead of full crossbar switches in combination with wavelength converters. We also show another design which can trade-off the switch cost with wavelength converter cost in this type of WDM optical interconnect.","PeriodicalId":177848,"journal":{"name":"Proceedings International Parallel and Distributed Processing Symposium","volume":"251 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117343426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Performance analysis of multilevel parallel applications on shared memory architectures 共享内存架构上多级并行应用程序的性能分析
Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213183
Gabriele Jost, Haoqiang Jin, Jesús Labarta, Judit Giménez, Jordi Caubet
{"title":"Performance analysis of multilevel parallel applications on shared memory architectures","authors":"Gabriele Jost, Haoqiang Jin, Jesús Labarta, Judit Giménez, Jordi Caubet","doi":"10.1109/IPDPS.2003.1213183","DOIUrl":"https://doi.org/10.1109/IPDPS.2003.1213183","url":null,"abstract":"In this paper we describe how to apply powerful performance analysis techniques to understand the behavior of multilevel parallel applications. We use the Paraver/OMPItrace performance analysis system for our study. This system consists of two major components: The OMPItrace dynamic instrumentation mechanism, which allows the tracing of processes and threads and the Paraver graphical user interface for inspection and analyses of the generated traces. We apply the system to conduct a detailed comparative study of a benchmark code implemented in five different programming paradigms applicable for shared memory computer architectures.","PeriodicalId":177848,"journal":{"name":"Proceedings International Parallel and Distributed Processing Symposium","volume":"23 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120852521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Wireless link layer enhancements for TCP and UDP applications 无线链路层增强TCP和UDP应用程序
Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213414
G. Xylomenos, George C. Polyzos
{"title":"Wireless link layer enhancements for TCP and UDP applications","authors":"G. Xylomenos, George C. Polyzos","doi":"10.1109/IPDPS.2003.1213414","DOIUrl":"https://doi.org/10.1109/IPDPS.2003.1213414","url":null,"abstract":"Internet application performance over wireless links is disappointing due to wireless impairments that adversely affect higher layers. This paper focuses on link layer enhancement mechanisms that hide wireless errors from the rest of the Internet. We simulated file transfer and WWW browsing over TCP and continuous media distribution over UDP, in conjunction with various link layer schemes. Our results reveal that WW browsing has substantially different behavior than file transfer, that existing TCP enhancement schemes have limited applicability and that UDP applications are best served by schemes inappropriate for TCP. Therefore, multiple link layer solutions are needed to optimize the performance of diverse applications.","PeriodicalId":177848,"journal":{"name":"Proceedings International Parallel and Distributed Processing Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121150996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
System level simulation of a SIMD active memory enhanced PC (or, why we don't want 100% bandwidth utilisation) SIMD活动内存增强PC的系统级模拟(或者，为什么我们不想要100%的带宽利用率)
Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213506
J. Mangnall, S. Quigley
{"title":"System level simulation of a SIMD active memory enhanced PC (or, why we don't want 100% bandwidth utilisation)","authors":"J. Mangnall, S. Quigley","doi":"10.1109/IPDPS.2003.1213506","DOIUrl":"https://doi.org/10.1109/IPDPS.2003.1213506","url":null,"abstract":"Merged logic and DRAM \"active memory\" or processing-in-memory (PIM) devices are widely recognised as a mechanism to avoid the memory wall bottlenecks exhibited by modern computing platforms. As several design efforts are working on commodity DRAM replacement parts, we present a simulation architecture for a SIMD active memory enhanced workstation. Additionally, we show that actually making use of all the available bandwidth presented by a DRAM to on-chip logic will significantly degrade the performance of an interactive multitasking environment. In order to minimise this performance degradation, we present a modified data tiling technique to allow the SIMD array's register file to be used as a cache.","PeriodicalId":177848,"journal":{"name":"Proceedings International Parallel and Distributed Processing Symposium","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127354677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new reconfigurable hardware architecture for high throughput networking applications and its design methodology 一种新的高吞吐量网络应用的可重构硬件体系结构及其设计方法
Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213337
M. Méribout, M. Motomura
{"title":"A new reconfigurable hardware architecture for high throughput networking applications and its design methodology","authors":"M. Méribout, M. Motomura","doi":"10.1109/IPDPS.2003.1213337","DOIUrl":"https://doi.org/10.1109/IPDPS.2003.1213337","url":null,"abstract":"Recent efforts to add new services to the Internet have increased the interest in designing flexible routers that are easy to extend and evolve. This paper describes a new hardware architecture based on dynamic reconfigurable logic (DRL) for high throughput networking applications. It mainly focuses on the content-based router and on how to schedule efficiently its computation time. This scheduling task is difficult because of the various features of the underlying hardware such as multicontext, control-data path architecture and memory interface. Experimental results show some improvements over most recent network processors as well as a better hardware synthesis methodology.","PeriodicalId":177848,"journal":{"name":"Proceedings International Parallel and Distributed Processing Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125071085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling parallel applications performance on heterogeneous systems 异构系统上并行应用程序性能建模
Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213298
J. Al-Jaroodi, N. Mohamed, Hong Jiang, D. Swanson
{"title":"Modeling parallel applications performance on heterogeneous systems","authors":"J. Al-Jaroodi, N. Mohamed, Hong Jiang, D. Swanson","doi":"10.1109/IPDPS.2003.1213298","DOIUrl":"https://doi.org/10.1109/IPDPS.2003.1213298","url":null,"abstract":"The current technologies have made it possible to execute parallel applications across heterogeneous platforms. However, the performance models available do not provide adequate methods to calculate, compare and predict the applications performance on these platforms. In this paper, we discuss an enhanced performance evaluation model for parallel applications on heterogeneous systems. In our analysis, we include machines of different architectures, specifications and operating environments. We also discuss the enabling technologies that facilitate such heterogeneous applications. The model is then validated through experimental measurements using an agent-based parallel Java system, which facilitates simultaneous utilization of heterogeneous systems for parallel applications. The model provides good evaluation metrics that allow developers to assess and compare the parallel heterogeneous applications performances.","PeriodicalId":177848,"journal":{"name":"Proceedings International Parallel and Distributed Processing Symposium","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123426315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Proximity and priority: applying a gene expression algorithm to the Traveling Salesperson Problem 邻近与优先:一种基因表达演算法应用于旅行推销员问题
Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213270
F. Burkowski
{"title":"Proximity and priority: applying a gene expression algorithm to the Traveling Salesperson Problem","authors":"F. Burkowski","doi":"10.1109/IPDPS.2003.1213270","DOIUrl":"https://doi.org/10.1109/IPDPS.2003.1213270","url":null,"abstract":"In this paper we describe an environment for evolutionary computation that supports the movement of information from genome to phenotype with the possibility of one or more intermediate transformations. Our notion of a phenotype is more than a simple alternate representation of the binary genome. The construction of a phenotype is sufficiently different from the genome as to require its generation by a procedure that we call a gene expression algorithm. We discuss various reasons why benefits should accrue when combining gene expression algorithms with conventional genetic algorithms and illustrate these ideas with an algorithm to generate approximate solutions to the traveling salesperson problem. As in most genetic algorithms dealing with the TSP we run into the problem of an appropriate crossover operation for the strings that specify a permutation. To handle this issue we introduce a novel genome representation that admits a natural crossover operation and produces a permutation vector as an intermediate representation.","PeriodicalId":177848,"journal":{"name":"Proceedings International Parallel and Distributed Processing Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123448062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Ad hoc networks: a protocol for supporting QoS applications 自组织网络:支持QoS应用程序的协议
Proceedings International Parallel and Distributed Processing Symposium Pub Date : 2003-04-22 DOI: 10.1109/IPDPS.2003.1213402
L. Donatiello, M. Furini
{"title":"Ad hoc networks: a protocol for supporting QoS applications","authors":"L. Donatiello, M. Furini","doi":"10.1109/IPDPS.2003.1213402","DOIUrl":"https://doi.org/10.1109/IPDPS.2003.1213402","url":null,"abstract":"A delay-bounded service in wireless ad hoc networks is challenging, as ad hoc networks do not provide any type of guarantees. Several protocols have been proposed to support applications without timing requirements in ad hoc networks, but the increasing demand of QoS applications, in ad hoc wireless environments, requires delay-bound service. The contribution of this paper is to propose a protocol that provides QoS service, by means of timing guarantees, to the supported applications in ad hoc wireless networks.","PeriodicalId":177848,"journal":{"name":"Proceedings International Parallel and Distributed Processing Symposium","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123470916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
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