System level simulation of a SIMD active memory enhanced PC (or, why we don't want 100% bandwidth utilisation)

Abstract

Merged logic and DRAM "active memory" or processing-in-memory (PIM) devices are widely recognised as a mechanism to avoid the memory wall bottlenecks exhibited by modern computing platforms. As several design efforts are working on commodity DRAM replacement parts, we present a simulation architecture for a SIMD active memory enhanced workstation. Additionally, we show that actually making use of all the available bandwidth presented by a DRAM to on-chip logic will significantly degrade the performance of an interactive multitasking environment. In order to minimise this performance degradation, we present a modified data tiling technique to allow the SIMD array's register file to be used as a cache.