ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors最新文献_第5页

Modeling and synthesis of communication subsystems for loop accelerator pipelines 环形加速器管道通信子系统建模与综合

ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2010-07-07 DOI: 10.1109/ASAP.2010.5540760

H. Dutta, Frank Hannig, Moritz Schmid, J. Keinert

引用次数: 3

ImpEDE: A multidimensional design-space exploration framework for biomedical-implant processors 阻碍:一个多维设计空间探索框架的生物医学植入处理器

ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2010-07-07 DOI: 10.1109/ASAP.2010.5540809

D. Dave, C. Strydis, G. Gaydadjiev

引用次数: 3

Design space exploration of parametric pipelined designs 参数化流水线设计的设计空间探索

ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2010-07-07 DOI: 10.1109/ASAP.2010.5540815

Adrien Le Masle, W. Luk

引用次数: 1

A pipelined camellia architecture for compact hardware implementation 一个流水线茶花架构紧凑的硬件实现

ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2010-07-07 DOI: 10.1109/ASAP.2010.5540987

E. Kavun, Tolga Yalçin

引用次数: 3

Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool 在c级为自动生成的硬件加速器优化DDR-SDRAM通信，体验Altera C2H HLS工具

ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2010-07-07 DOI: 10.1109/ASAP.2010.5540967

Christophe Alias, A. Darte, Alexandru Plesco

{"title":"Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool","authors":"Christophe Alias, A. Darte, Alexandru Plesco","doi":"10.1109/ASAP.2010.5540967","DOIUrl":"https://doi.org/10.1109/ASAP.2010.5540967","url":null,"abstract":"Thanks to efficient scheduling, resource sharing, and finite-state machines generation, high-level synthesis (HLS) tools are now more mature for generating hardware accelerators with an optimized internal structure. But interfacing them within the complete design, with optimized communications, to achieve the best throughput remains hard. Expert designers still need to program all the necessary glue (in VHDL/Verilog) to get an efficient design. Taking the example of C2H, the Altera HLS tool, and of accelerators communicating to an external DDR memory, we show it is possible to restructure the application code, to generate adequate communication processes, in C, and to compile them all with C2H, so that the resulting application is highly-optimized, with full usage of the memory bandwidth. In other words, our study demonstrates that HLS tools can be used as back-end optimizers for front-end optimizations, as it is the case for standard compilation with high-level transformations developed on top of assembly-code optimizers. We believe this is the way to go for making HLS tools viable.","PeriodicalId":175846,"journal":{"name":"ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134471173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Comparing the robustness of fault-tolerant enhancements when applied to lookup tables and random logic for nano-computing 比较应用于查找表和纳米计算的随机逻辑时容错增强的健壮性

ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2010-07-07 DOI: 10.1109/ASAP.2010.5540775

Y. Dotan, Orgad Chen, Gil Katz

{"title":"Comparing the robustness of fault-tolerant enhancements when applied to lookup tables and random logic for nano-computing","authors":"Y. Dotan, Orgad Chen, Gil Katz","doi":"10.1109/ASAP.2010.5540775","DOIUrl":"https://doi.org/10.1109/ASAP.2010.5540775","url":null,"abstract":"New challenges are arising in the design of computer systems with the emergence of new nanometer-scale devices and sophisticated fabrication techniques. Unfortunately, the yield, reliability, and drive characteristics of these new deep-submicron and nano-scale devices are different from the corresponding characteristics of conventional CMOS devices. It is expected that future circuit technologies will have substantially higher defect densities and dynamic fault rates. There is no consensus yet on which technology will be selected and which of the traditional logic designs has an advantage for fault tolerant nano-computing. In this work, we compare the robustness of several fault-tolerant approaches applied to lookup table design and random logic design for a wide range of fault rates. Implementing fault tolerance in a circuit using TMR and Hamming and Hsiao error correcting codes with a lookup table design style gives better fault coverage compared with a random gate design style. TMR is the best fault-tolerance technique when implemented using the lookup table design. However, TMR was the worst technique for fault rates greater than 0.5% when implemented using random logic design and no gate level is fault free.","PeriodicalId":175846,"journal":{"name":"ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134490871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Power dissipation challenges in multicore floating-point units 多核浮点单元的功耗挑战

ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2010-07-07 DOI: 10.1109/ASAP.2010.5540986

Wei Liu, A. Nannarelli

引用次数: 6

Potential of using block floating point arithmetic in ASIP-based GNSS-receivers 在基于ip的gnss接收机中使用块浮点算法的潜力

ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2010-07-07 DOI: 10.1109/ASAP.2010.5540988

E. Tasdemir, G. Kappen, T. Noll

引用次数: 3

A C++-embedded Domain-Specific Language for programming the MORA soft processor array 一种用于MORA软处理器阵列编程的c++嵌入式领域特定语言

ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2010-07-07 DOI: 10.1109/ASAP.2010.5540750

W. Vanderbauwhede, M. Margala, S. R. Chalamalasetti, Sohan Purohit

引用次数: 12