Comparing the robustness of fault-tolerant enhancements when applied to lookup tables and random logic for nano-computing

Abstract

New challenges are arising in the design of computer systems with the emergence of new nanometer-scale devices and sophisticated fabrication techniques. Unfortunately, the yield, reliability, and drive characteristics of these new deep-submicron and nano-scale devices are different from the corresponding characteristics of conventional CMOS devices. It is expected that future circuit technologies will have substantially higher defect densities and dynamic fault rates. There is no consensus yet on which technology will be selected and which of the traditional logic designs has an advantage for fault tolerant nano-computing. In this work, we compare the robustness of several fault-tolerant approaches applied to lookup table design and random logic design for a wide range of fault rates. Implementing fault tolerance in a circuit using TMR and Hamming and Hsiao error correcting codes with a lookup table design style gives better fault coverage compared with a random gate design style. TMR is the best fault-tolerance technique when implemented using the lookup table design. However, TMR was the worst technique for fault rates greater than 0.5% when implemented using random logic design and no gate level is fault free.