2014 24th International Conference on Field Programmable Logic and Applications (FPL)最新文献_第8页

Enabling SRAM-PUFs on Xilinx FPGAs

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927384

A. Wild, T. Güneysu

引用次数: 18

Source-level debugging for FPGA high-level synthesis FPGA 高级综合的源代码级调试

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927496

Nazanin Calagar, S. Brown, J. Anderson

引用次数: 65

An efficient FPGA-based hardware framework for natural feature extraction and related Computer Vision tasks 基于fpga的自然特征提取及相关计算机视觉任务的高效硬件框架

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927463

Matthias Pohl, M. Schaeferling, G. Kiefer

{"title":"An efficient FPGA-based hardware framework for natural feature extraction and related Computer Vision tasks","authors":"Matthias Pohl, M. Schaeferling, G. Kiefer","doi":"10.1109/FPL.2014.6927463","DOIUrl":"https://doi.org/10.1109/FPL.2014.6927463","url":null,"abstract":"The paper presents an efficient and flexible framework for extensive image processing tasks. While most available frameworks concentrate on pixel-based modules and interfaces for image preprocessing tasks, our proposal also covers the seamless integration of higher-level algorithms. Window-oriented filter operations, such as noise filters, edge filters or natural feature detectors, are performed within an efficient 2D window pipeline. This structure is generated and optimized automatically based on a user-defined filter configuration. For complex, higher-level algorithms, an optimized array of independent, software-based processing units is generated. As an example application, we chose object recognition based on the well-known SURF algorithm (“Speeded Up Robust Features”), which performs natural feature detection and description. All involved image processing steps were successfully mapped to our architecture. Thus, exploiting the FPGAs full potential regarding parallelism, we synthesized one of the most efficient SURF detectors and a complete object recognition system in a single mid-size FPGA.","PeriodicalId":172795,"journal":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129620039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A highly-efficient and green data flow engine for solving euler atmospheric equations 求解欧拉大气方程的高效绿色数据流引擎

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927462

L. Gan, H. Fu, Chao Yang, W. Luk, Wei Xue, O. Mencer, Xiaomeng Huang, Guangwen Yang

{"title":"A highly-efficient and green data flow engine for solving euler atmospheric equations","authors":"L. Gan, H. Fu, Chao Yang, W. Luk, Wei Xue, O. Mencer, Xiaomeng Huang, Guangwen Yang","doi":"10.1109/FPL.2014.6927462","DOIUrl":"https://doi.org/10.1109/FPL.2014.6927462","url":null,"abstract":"Atmospheric modeling is an essential issue in the study of climate change. However, due to the complicated algorithmic and communication models, scientists and researchers are facing tough challenges in finding efficient solutions to solve the atmospheric equations. In this paper, we accelerate a solver for the three-dimensional Euler atmospheric equations through reconfigurable data flow engines. We first propose a hybrid design that achieves efficient resource allocation and data reuse. Furthermore, through algorithmic offsetting, fast memory table, and customizable-precision arithmetic, we map a complex Euler kernel into a single FPGA chip, which can perform 956 floating point operations per cycle. In a 1U-chassis, our CPU-DFE unit with 8 FPGA chips is 18.5 times faster and 8.3 times more power efficient than a multicore system based on two 12-core Intel E5-2697 (Ivy Bridge) CPUs, and is 6.2 times faster and 5.2 times more power efficient than a hybrid unit equipped with two 12-core Intel E5-2697 (Ivy Bridge) CPUs and three Intel Xeon Phi 5120d (MIC) cards.","PeriodicalId":172795,"journal":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125518277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security 在基于树的FPGA中平衡WDDL双轨逻辑，增强物理安全性

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927422

Emna Amouri, S. Bhasin, Y. Mathieu, T. Graba, J. Danger, H. Mehrez

引用次数: 5

An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications 一种实时应用的horn - schunck光流算法的fpga优化架构

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927406

Michael Kunz, Alexander Ostrowski, P. Zipf

引用次数: 23

FPGA implementation of a multi-algorithm parallel FEC for SDR platforms SDR平台上多算法并行FEC的FPGA实现

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927446

Zhenzhi Wu, Dake Liu, Zheng Yang, Qingying Wang, Wei Zhou

引用次数: 2

Using high-level knowledge to enhance data channels in FPGA streaming systems 利用高级知识增强FPGA流系统中的数据通道

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927381

Marlon Wijeyasinghe, David B. Thomas

{"title":"Using high-level knowledge to enhance data channels in FPGA streaming systems","authors":"Marlon Wijeyasinghe, David B. Thomas","doi":"10.1109/FPL.2014.6927381","DOIUrl":"https://doi.org/10.1109/FPL.2014.6927381","url":null,"abstract":"FPGAs are commonly used in high performance computing applications, often in the form of streaming systems which exploit parallelism of algorithms along pipelined kernels. While such applications have traditionally been designed at the Register Transfer Level (RTL), the increasing complexity in terms of FPGA resource usage, arithmetic logic and dataflow is causing the time taken for RTL programming to be prohibitive. This necessitates using high-level programming tools to transparently handle low-level aspects - thus simplifying the design process. Examples of high-level tools for building streaming systems include MaxCompiler by Maxeler Technologies and DSP Builder by Altera. We propose an interception layer which when inserted into communication channels, transparently enhances their performance and capabilities without needing to modify the streaming kernels or host code. We discuss specific channel enhancements: lossless compression to improve effective bandwidth; error correction and fault tolerance to improve reliability. The interception layer is intended to add complex behaviour while maintaining the simplicity of the high-level abstraction when transmitting data via a channel.","PeriodicalId":172795,"journal":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129486577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy 利用硬件冗余提高基于sram网格的集群FPGA的缺陷容忍度

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927389

Adrien Blanchardon, R. Chotin-Avot, H. Mehrez, Emna Amouri

{"title":"Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy","authors":"Adrien Blanchardon, R. Chotin-Avot, H. Mehrez, Emna Amouri","doi":"10.1109/FPL.2014.6927389","DOIUrl":"https://doi.org/10.1109/FPL.2014.6927389","url":null,"abstract":"The technological evolution involves a higher number of physical defects in circuits after manufacturing. One of the future challenge is to find a way to use a maximum of defected manufactured circuits. In this paper, multiple techniques are proposed to avoid defects in the cluster local interconnect of a SRAM-based Mesh of Clusters FPGA. Using defect tolerance, area and timing metrics, two previous hardware redundancy strategies are evaluated on the Mesh of Clusters architecture : Fine Grain Redundancy (FGR) and Improved Fine Grain Redundancy (IFGR). We show that using these techniques on a cluster of a Mesh of Clusters architecture permits to tolerate 8 times more defects than on an industrial Mesh FPGA with a low area overhead (-6% for FGR and 22% for IFGR) and a low increase of Critical Path Delay (CPD)(6% for FGR and 2% for IFGR). We also proposed three new redundancy strategies using spare resources : Distributed Feedbacks (DF) for crossbar down, Adapted Fine Grain Redundancy (AFGR) to avoid defective multiplexers and Upward Redundant Multiplexer (URM) for the crossbar up. Compared to the Mesh of Clusters architecture without defect tolerance techniques, the best trade off between defect tolerance (36.4%), area overhead (11.56%) and CPD (+7.46%) is obtained using AFGR. Using the other methods permits to considerably limit the area overhead (10.4% with URM) with a lesser number of defective elements bypassed (18% max).","PeriodicalId":172795,"journal":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130042235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Incremental distributed trigger insertion for efficient FPGA debug 增量分布式触发器插入高效FPGA调试

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927418

F. Eslami, S. Wilton

引用次数: 11