2014 24th International Conference on Field Programmable Logic and Applications (FPL)最新文献_第7页

An image processing library for C-based high-level synthesis 基于c语言的高级合成图像处理库

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927424

Moritz Schmid, Nicolas Apelt, Frank Hannig, J. Teich

引用次数: 27

Methods for implementation of feedback loops in high speed FPGA applications 在高速FPGA应用中实现反馈回路的方法

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927434

Nima Safari, V. Mauer, S. Gheitanchi

引用次数: 0

Efficient implementation of a single-precision floating-point arithmetic unit on FPGA 单精度浮点运算单元在FPGA上的高效实现

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927391

Wilson Jose, Ana Rita Silva, H. Neto, M. Véstias

引用次数: 9

Asynchronously assisted FPGA for variability 异步辅助FPGA可变性

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927398

H. S. Low, D. Shang, Fei Xia, A. Yakovlev

引用次数: 3

Aging effects in FPGAs: an experimental analysis fpga老化效应的实验分析

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927390

A. Amouri, Florent Bruguier, S. Kiamehr, P. Benoit, L. Torres, M. Tahoori

{"title":"Aging effects in FPGAs: an experimental analysis","authors":"A. Amouri, Florent Bruguier, S. Kiamehr, P. Benoit, L. Torres, M. Tahoori","doi":"10.1109/FPL.2014.6927390","DOIUrl":"https://doi.org/10.1109/FPL.2014.6927390","url":null,"abstract":"Modern Field Programmable Gate Arrays (FPGAs) are built using the most advanced technology nodes to meet performance and power demands. This makes them susceptible to various reliability challenges at nano-scale, and in particular to transistor aging. In this paper, an experimental analysis is made to identify the main parameters and phenomena influencing the performance degradation of FPGAs. For that purpose, a set of controlled ring-oscillator-based sensors with different frequencies and tunable activity control are implemented on a Spartan-6 FPGA. Thus, the internal switching activities (SAs) and signal probabilities (SPs) of the sensors can be varied. We performed accelerated-lifetime conditions using elevated temperatures and voltages in a controlled setting to stress the FPGA. A novel monitoring method based on measuring the electromagnetic emissions of the FPGA is used to accurately monitor the performance of the sensors before and after the stress. The experiments reveal the extent of performance degradations, the impact of SPs and SAs, and the relative impacts of BTI and HCI aging factors.","PeriodicalId":172795,"journal":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129342987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

FPGA architecture support for heterogeneous, relocatable partial bitstreams FPGA架构支持异构、可重定位的部分位流

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927494

Christophe Huriaux, O. Sentieys, R. Tessier

{"title":"FPGA architecture support for heterogeneous, relocatable partial bitstreams","authors":"Christophe Huriaux, O. Sentieys, R. Tessier","doi":"10.1109/FPL.2014.6927494","DOIUrl":"https://doi.org/10.1109/FPL.2014.6927494","url":null,"abstract":"The use of partial dynamic reconfiguration in FPGA-based systems has grown in recent years as the spectrum of applications which use this feature has increased. For these systems, it is desirable to create a series of partial bitstreams which represent tasks which can be located in multiple regions in the FPGA fabric. While the transferal of homogeneous collections of lookup-table based logic blocks from region to region has been shown to be relatively straightforward, it is more difficult to transfer partial bitstreams which contain fixed-function resources, such as block RAMs and DSP blocks. In this paper we consider FPGA architecture enhancements which allow for the migration of partial bitstreams including fixed-function resources from region to region even if these resources are not located in the same position in each region. Our approach does not require significant, time-consuming place-and-route during the migration process. We quantify the cost of inserting additional routing resources into the FPGA architecture to allow for easy migration of heterogeneous, fixed-function resources. Our experiments show that this flexibility can be added for a relatively low overhead and performance penalty.","PeriodicalId":172795,"journal":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","volume":"293 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115079021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Mixed-architecture process scheduling on tightly coupled reconfigurable computers 紧耦合可重构计算机上的混合体系结构进程调度

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927421

B. K. Hamilton, M. Inggs, Hayden Kwok-Hay So

引用次数: 7

FPGA implementation of an interior point method for high-speed model predictive control FPGA实现的一种内点法高速模型预测控制

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927473

Junyi Liu, Helfried Peyrl, A. Burg, G. Constantinides

引用次数: 13

Efficient mapping of mathematical expressions into DSP blocks 有效的数学表达式映射到DSP块

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927419

Bajaj Ronak, Suhaib A. Fahmy

引用次数: 16

Efficient 3D triangulation in hardware for dense structure-from-motion in low-speed automotive scenarios 针对低速汽车场景中密集运动结构的硬件高效三维三角测量

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927465

S. Wonneberger, Max Kohler, W. Derendarz, T. Graf, Rolf Ernst

{"title":"Efficient 3D triangulation in hardware for dense structure-from-motion in low-speed automotive scenarios","authors":"S. Wonneberger, Max Kohler, W. Derendarz, T. Graf, Rolf Ernst","doi":"10.1109/FPL.2014.6927465","DOIUrl":"https://doi.org/10.1109/FPL.2014.6927465","url":null,"abstract":"With the introduction of surround view cameras in modern vehicles and the possibility of calculating dense motion fields in real-time from a moving camera a detailed 3D reconstruction of the static environment is possible (structure-from-motion). Beside the necessity of a motion field between two image frames the task of triangulating those individual 2D point matches to 3D points in the world becomes non real-time on modern CPUs when to be repeated for all image points. In this work we evaluate different approaches to the 3D triangulation optimization problem in a typical structure-from-motion processing chain for an efficient implementation in hardware. An architecture for solving this problem using linear triangulation with an inhomogeneous solution to the equation system is proposed. We evaluate our implementation using FPGAs against a software-implementation with synthetic datasets and from low-speed parking area scenes for numerical accuracy and real-time capabilities. In addition the proposed fixed-point arithmetic implementation is compared against an implementation using floating-point units.","PeriodicalId":172795,"journal":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125903201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2