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Empirical Analysis of Disaggregated Cloud Memory on Memory Intensive Applications 分类云内存在内存密集型应用中的实证分析
4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-10-31 DOI: 10.5573/jsts.2023.23.5.273
Yeonwoo Jeong, Gyeonghwan Jung, Kyuli Park, Youngjae Kim, Sungyong Park
{"title":"Empirical Analysis of Disaggregated Cloud Memory on Memory Intensive Applications","authors":"Yeonwoo Jeong, Gyeonghwan Jung, Kyuli Park, Youngjae Kim, Sungyong Park","doi":"10.5573/jsts.2023.23.5.273","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.5.273","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136017876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 20-Gb/s PAM-4 Receiver with Dual-mode Threshold Voltage Adaptation using a Time-based LSB Decoder 基于时基LSB解码器的20 gb /s双模阈值电压自适应PAM-4接收机
4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-10-31 DOI: 10.5573/jsts.2023.23.5.303
Jeong-Mi Park, Jin-Ku Kang
{"title":"A 20-Gb/s PAM-4 Receiver with Dual-mode Threshold Voltage Adaptation using a Time-based LSB Decoder","authors":"Jeong-Mi Park, Jin-Ku Kang","doi":"10.5573/jsts.2023.23.5.303","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.5.303","url":null,"abstract":"This paper presents a pulse amplitude modulation-4 (PAM-4) receiver with dual-mode threshold voltage applied to a time-based LSB decoder. The proposed receiver can select the threshold voltage that improves the robustness to sampler voltage variations. It also presents a random data-based threshold voltage adaptation using a single error sampler. Compared to the conventional PAM-4 threshold voltage adaptation that finds four data levels, this method finds only two levels, which reduces the overall power consumption, hardware complexity and adaptation time. The 20-Gb/s PAM-4 serial link was designed in a 65 nm CMOS Technology and analyzed with XMODEL and Cadence Design System","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136018003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Resistive Hydrogen Detection Sensors based on 2 Dimensions – Molybdenum Disulfide Decorated by Palladium Nanoparticles 基于二维钯纳米粒子修饰二硫化钼的电阻式氢探测传感器
4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-10-31 DOI: 10.5573/jsts.2023.23.5.258
DongJun Jang, U-Jin Cho, Youhyeong Jeon, TaeYong Lee, RyangHa Kim, Younglae Kim, Min-Woo Kwon
{"title":"Resistive Hydrogen Detection Sensors based on 2 Dimensions – Molybdenum Disulfide Decorated by Palladium Nanoparticles","authors":"DongJun Jang, U-Jin Cho, Youhyeong Jeon, TaeYong Lee, RyangHa Kim, Younglae Kim, Min-Woo Kwon","doi":"10.5573/jsts.2023.23.5.258","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.5.258","url":null,"abstract":"This research presents a resistive-type hydrogen (HSUB2/SUB) gas sensor based on a composite of palladium nanoparticles (Pd-NP) decorated on 2Dmolybdenum disulfide (MoS2) layer. The sensor fabrication involves synthesizing MoSSUB2/SUB and coating Pd by DC sputtering technique. MoS2 has been adopted for its high selectivity for H2, wide operating temperature range, reliability, and low power consumption. Pd has high catalytic properties for HSUB2/SUB and performs a HSUB2/SUB adsorption mechanism through resistance transition. In this study, we propose a Pddecorated MoS2 structure and introduce the chemical resistance mechanism within the channel. The limit of detection (LOD), sensitivity and response time of the fabricated HSUB2/SUB gas sensors are optimized and analyzed. Finally, the nanocomposites network based HSUB2/SUB sensor can promote the utilization of various industries and discuss the issues in sensor applications.","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136018004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Charge Trap Flash structure with Feedback Field Effect Transistor for Processing in Memory 带反馈场效应晶体管的电荷阱闪光结构在存储器中的处理
4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-10-31 DOI: 10.5573/jsts.2023.23.5.295
Junhyeong Lee, Misun Cha, Min-Woo Kwon
{"title":"Charge Trap Flash structure with Feedback Field Effect Transistor for Processing in Memory","authors":"Junhyeong Lee, Misun Cha, Min-Woo Kwon","doi":"10.5573/jsts.2023.23.5.295","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.5.295","url":null,"abstract":"Recently, a memory wall has become a concern due to the increasing distance between memory and CPU in the von Neumann structure. While the CPU and logic devices operate quickly, their speed becomes irrelevant due to the slow data transfer between them. Consequently, addressing the data delay problem between the CPU and the logic elements is crucial. To tackle this issue, researchers have been exploring the Processing in Memory (PIM) technology, which enables simultaneous memory and computation. However, traditional volatile or nonvolatile memory-based PIM approaches have inherent limitations in overcoming the memory wall problem, as memory and computation are performed sequentially on separate devices. Therefore, there is a need to develop a new memory-logic device capable of performing read and operation simultaneously. In this paper, we propose a Feedback Field Effect Transistor (FBFET) with a charge trap layer that can fulfill both memory and computational roles, thus implementing an ideal Processing in Memory technology. The device features an oxide-nitride-oxide structure, where nitride is coupled to the oxide side of the FBFET. It accumulates electric charges in the floating body for memory operations and reads the data stored in the charge trap layer for logic operations. By selecting the control gate bias, the computing operation can be configured to perform AND or OR operations. This enables simultaneous memory and logical operations to take place.","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136018005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 97.7-dB DR 12.3-μW 1-kHz Bandwidth 2<SUP>nd</SUP> Order Delta-sigma Modulator with a Fully Differential Class-AB Op-Amp using Floating Class-AB Control 97.7 db DR 12.3 μ w 1 khz带宽2&lt;SUP&gt; and &lt;/SUP&gt;阶Delta-sigma调制器，带全差分ab类运算放大器，采用浮动ab类控制
4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-10-31 DOI: 10.5573/jsts.2023.23.5.265
Byeong-Ho Yu, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Gil-Cho Ahn
{"title":"A 97.7-dB DR 12.3-μW 1-kHz Bandwidth 2&lt;SUP&gt;nd&lt;/SUP&gt; Order Delta-sigma Modulator with a Fully Differential Class-AB Op-Amp using Floating Class-AB Control","authors":"Byeong-Ho Yu, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Gil-Cho Ahn","doi":"10.5573/jsts.2023.23.5.265","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.5.265","url":null,"abstract":"This paper presents a 2SUPnd/SUP order modified feed-forward (FF) delta-sigma modulator. To reduce power consumption, the proposed analog-to-digital converter (ADC) adopts a class-AB op-amp for the first integrator since it shows an enhanced slew rate with low quiescent current. In addition, a 4-bit asynchronous successive approximation register (SAR) ADC which exhibits low power consumption is employed as a quantizer. A delay is incorporated into the feedback path for stable operation of the feedback loop. The prototype ADC is fabricated in a 28 nm CMOS process, and the core area is 0.095 mm2. It consumes 12.3 μW from 0.8 V (Analog)/0.85 V (Digital) supply voltages at an operating clock frequency of 512 kHz with an oversampling ratio (OSR) of 256. It achieves a dynamic range (DR) of 97.7 dB and a peak signal-to-noise and distortion ratio (SNDR) of 94.8 dB, corresponding to a Schreier figure-of-merit (FoM) of 176.8 dB.","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136017533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-power Incremental Delta-sigma ADC with Adaptive Biasing for CMOS Image Sensors 用于CMOS图像传感器的低功耗增量Delta-sigma自适应偏置ADC
4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-10-31 DOI: 10.5573/jsts.2023.23.5.314
Dong-Hwan Seo, Jung-Gyun Kim, Byung-Geun Lee
{"title":"A Low-power Incremental Delta-sigma ADC with Adaptive Biasing for CMOS Image Sensors","authors":"Dong-Hwan Seo, Jung-Gyun Kim, Byung-Geun Lee","doi":"10.5573/jsts.2023.23.5.314","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.5.314","url":null,"abstract":"This paper presents the design and fabrication of a low-power incremental delta-sigma analog-to-digital converter (ADC) with an adaptive bias technique suitable for complimentary metaloxide semiconductor (CMOS) image sensors (CISs). The adaptive biasing circuitry provides the amplifier with a predicted minimum current value required for the integrator output to settle; this optimized current flows through the amplifier and reduces power consumption by 40%. A prototype ADC fabricated using a 0.18 μm CMOS process, achieves an SNDR of 65 dB at a sampling frequency of 25 MHz and consumes 13.5 μW from a 1.8 V power supply. The measured differential and integral nonlinearities are +0.31/-0.42 and +0.62/-0.75 at a 12-bit accuracy, respectively.","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136018006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Deep Learning Segmentation Modeling for SiN, SiO<SUB>2</SUB> Film Deposition Process Defect of High Bandwidth Memory 深度学习分割建模的SiN, SiO&lt;SUB&gt;2&lt;/SUB&gt;高带宽存储器薄膜沉积工艺缺陷
4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-10-31 DOI: 10.5573/jsts.2023.23.5.251
Intae Whoang, Chinkwan Cho, Jin-Hee Hong, Dong-Hee Son, Byung-Yoon Lim, Jin-Pyung Kim, Kijun Bang
{"title":"Deep Learning Segmentation Modeling for SiN, SiO&lt;SUB&gt;2&lt;/SUB&gt; Film Deposition Process Defect of High Bandwidth Memory","authors":"Intae Whoang, Chinkwan Cho, Jin-Hee Hong, Dong-Hee Son, Byung-Yoon Lim, Jin-Pyung Kim, Kijun Bang","doi":"10.5573/jsts.2023.23.5.251","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.5.251","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136017873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study on the Circuit Performance of Various Interconnect Metal Materials in the Latest Process Nodes 各种互连金属材料在最新工艺节点中的电路性能研究
IF 0.4 4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-08-31 DOI: 10.5573/jsts.2023.23.4.215
Moonjeong Choi, Juhwan Park, Seoungyeol Choi, K. Kwon, Yeji Lee, Wonyeong Jang, Jongwook Jeon
{"title":"Study on the Circuit Performance of Various Interconnect Metal Materials in the Latest Process Nodes","authors":"Moonjeong Choi, Juhwan Park, Seoungyeol Choi, K. Kwon, Yeji Lee, Wonyeong Jang, Jongwook Jeon","doi":"10.5573/jsts.2023.23.4.215","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.4.215","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2023-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87756921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Lightweight Scan Architecture against the Scan-based Side-channel Attack 针对基于扫描的侧信道攻击的轻量级扫描架构
IF 0.4 4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-08-31 DOI: 10.5573/jsts.2023.23.4.243
Xiangqi Wang, Xingxing Gong, Xianmin Pan, Weizheng Wang
{"title":"A Lightweight Scan Architecture against the Scan-based Side-channel Attack","authors":"Xiangqi Wang, Xingxing Gong, Xianmin Pan, Weizheng Wang","doi":"10.5573/jsts.2023.23.4.243","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.4.243","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2023-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85938494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effects of Material and Doping Profile Engineering of Source Junction on Line Tunneling FET Operations 源结材料和掺杂剖面工程对线隧穿场效应管工作的影响
IF 0.4 4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-08-31 DOI: 10.5573/jsts.2023.23.4.228
Min-Ki Ko, Jang-Hyun Kim, Garam Kim
{"title":"Effects of Material and Doping Profile Engineering of Source Junction on Line Tunneling FET Operations","authors":"Min-Ki Ko, Jang-Hyun Kim, Garam Kim","doi":"10.5573/jsts.2023.23.4.228","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.4.228","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2023-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84753631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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