2013 13th International Conference on Application of Concurrency to System Design最新文献

{"title":"Incremental Generation of Linear Invariants for Component-Based Systems","authors":"S. Bensalem, M. Bozga, B. Boyer, Axel Legay","doi":"10.1109/ACSD.2013.11","DOIUrl":"https://doi.org/10.1109/ACSD.2013.11","url":null,"abstract":"Invariants generation has been intensively considered as an effective verification method for concurrent systems. However, none of the existing work on the topic strongly exploits the structure of the system and the algebra that defines the interactions between its components. This not only has an impact on the computation time, but also on the scalability of the method. In a series of recent work, we developed an efficient approach for generating invariants for systems described in the BIP component framework. BIP is an expressive modeling formalism including a rich algebra to describe component interactions. Our technique, which focuses on generating Boolean invariants corresponding to a subclass of the conjunctive normal form, was then extended to an incremental one capable of generating global invariants from smaller invariants obtained for sub-systems by exploiting the algebra that describes their interactions. This approach gives a panoply of techniques and libraries to rigorously design potentially complex systems. We also showed that Boolean invariants generated by our methodology correspond to trap of the Petri net induced by the BIP model. Unfortunately, this class of invariants may be too imprecise, and hence leads to discovery of false positive counter examples. The objective of this paper is to propose new techniques dedicated to the computation of linear interactions invariants, i.e., invariants that are described by linear constraints and that relate states of several components in the system. By definition, such new class is incomparable to the one of Boolean invariants, but we will show that it is generally more precise. In addition, we propose an incremental approach that allows to discover and reuse invariants that have already been computed on subparts of the model. Those new techniques have been implemented in DFINDER, a tool for checking deadlock freedom on BIP systems using invariants, and evaluated on several case studies. The experiments show that our approach outperforms classical techniques on a wide range of models.","PeriodicalId":166715,"journal":{"name":"2013 13th International Conference on Application of Concurrency to System Design","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121051610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lexicographical Generations of Combined Traces","authors":"Lukasz Mikulski, Marcin Piatkowski, Sebastian Smyczynski","doi":"10.1109/ACSD.2013.24","DOIUrl":"https://doi.org/10.1109/ACSD.2013.24","url":null,"abstract":"Combined traces are intrinsic mathematical model for studying concurrent systems behaviors. They can be used to describe and investigate processes of elementary net systems with inhibitor arcs and allow to describe weak causality and simultaneity of actions. We provide several algorithms for manipulating combined traces using their language theoretic representations. In particular, we propose two methods of enumeration related to combined traces, supported by a collection of auxiliary procedures. First, for a specified combined trace we iterate the set of all its representatives (namely step sequences). Next, we use the lexicographical order on step sequences to list all combined traces of a fixed size. We also discuss the time complexity of all presented algorithms.","PeriodicalId":166715,"journal":{"name":"2013 13th International Conference on Application of Concurrency to System Design","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128454215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On Cyclic Behaviour of Unbounded Petri Nets","authors":"J. Desel","doi":"10.1109/ACSD.2013.14","DOIUrl":"https://doi.org/10.1109/ACSD.2013.14","url":null,"abstract":"Cycles in state spaces represent repetitive behaviour of system models. Runs reproducing some state have important interpretations, for example rounds in distributed algorithms. In case of unbounded system models with infinite state space, cycles cannot be found in a straightforward way. For Petri nets, transition invariants provide necessary conditions for cyclic behaviour, but not for every transition invariant there is a corresponding cycle. Another approach to deal with infinite state behaviour is to consider finite coverability graphs which generalize reachability graphs by adding the value \"arbitrary many\" for unbounded places. Unfortunately, a cycle in the coverability graph does not necessarily represent a cyclic behaviour. This paper combines the concepts transition invariant and coverability graph in such a way that cyclic behaviour can be found in a combined graph. This implies a way to decide whether a sequence constitutes a cycle. A finite representation of all (infinitely many) cycles is implied by a result stating that the set of cycles is semi-linear. We also discuss an application of this concept: schedulability of Petri nets, i.e., control of transition occurrences such that the controlled behaviour does not lead to arbitrary token growth on any place.","PeriodicalId":166715,"journal":{"name":"2013 13th International Conference on Application of Concurrency to System Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126168445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Parametric Tool for Applied Process Calculi","authors":"J. Borgström, Ramunas Gutkovas, Ioana Rodhe, B. Victor","doi":"10.1109/ACSD.2013.22","DOIUrl":"https://doi.org/10.1109/ACSD.2013.22","url":null,"abstract":"High-level formalisms for concurrency are often defined as extensions of the the pi-calculus, a growing number is geared towards particular applications or computational paradigms. Psi-calculi is a parametric framework that can accommodate a wide spectrum of such calculi. It allows the definition of process calculi that extend the pi-calculus with arbitrary data, logic and logical assertions. All such psi calculi inherit machine- checked proofs of the meta-theory such as compositionality and bisimulation congruence. We present a generic tool for analysing processes from any psi calculus instance, and for implementing new instances with the help of a supporting library. The tool implements symbolic execution and bisimulation algorithms for both unicast and wireless broadcast communication. We illustrate the tool by examples from pi-calculus and the area of wireless sensor networks.","PeriodicalId":166715,"journal":{"name":"2013 13th International Conference on Application of Concurrency to System Design","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131053303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"STG-Based Resynthesis for Balsa Circuits","authors":"Stanislavs Golubcovs, W. Vogler, Norman Kluge","doi":"10.1109/ACSD.2013.17","DOIUrl":"https://doi.org/10.1109/ACSD.2013.17","url":null,"abstract":"Balsa provides a rapid development flow, where asynchronous circuits are created from high-level specifications, but the syntax-driven translation used by the Balsa compiler often results in performance overhead. To reduce this performance penalty, various control resynthesis and peephole optimization techniques are used, in this paper, STG-based resynthesis is considered. For this, we have translated the control parts of all components used by the Balsa compiler into STGs. A Balsa specification corresponds to the parallel composition of such STGs, but this composition must be reduced. We have developed new reduction operations and, using real-life examples, studied various strategies how to apply them.","PeriodicalId":166715,"journal":{"name":"2013 13th International Conference on Application of Concurrency to System Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125131392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tag Machines for Modeling Heterogeneous Systems","authors":"Thi Thieu Hoa Le, R. Passerone, U. Fahrenberg, Axel Legay","doi":"10.1109/ACSD.2013.23","DOIUrl":"https://doi.org/10.1109/ACSD.2013.23","url":null,"abstract":"Embedded systems are often composed from components of very different natures, e.g., mechanical and electronic. Composition of heterogeneous components is generally not well-defined, making design and verification difficult. Denotational mathematical frameworks for reasoning effectively on heterogeneous composition have recently been made available. In this work, we propose an operational version of this formalism, based on tag machines, that can represent heterogeneous composition, and we provide conditions under which the heterogeneous composition can be captured soundly and completely. We have implemented our operational framework in a prototype tool which we use for experimental evaluation.","PeriodicalId":166715,"journal":{"name":"2013 13th International Conference on Application of Concurrency to System Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117111092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Programming and Timing Analysis of Parallel Programs on Multicores","authors":"Eugene Yip, P. Roop, M. Biglari-Abhari, A. Girault","doi":"10.1109/ACSD.2013.19","DOIUrl":"https://doi.org/10.1109/ACSD.2013.19","url":null,"abstract":"Multicore processors provide better power-performance trade-offs compared to single-core processors. Consequently, they are rapidly penetrating market segments which are both safety critical and hard real-time in nature. However, designing time-predictable embedded applications over multicores remains a considerable challenge. This paper proposes the ForeC language for the deterministic parallel programming of embedded applications on multicores. ForeC extends C with a minimal set of constructs adopted from synchronous languages. To guarantee the worst-case performance of ForeC programs, we offer a very precise reachability-based timing analyzer. To the best of our knowledge, this is the first attempt at the efficient and deterministic parallel programming of multicores using a synchronous C-variant. Experimentation with large multicore programs revealed an average over-estimation of only 2% for the computed worst-case execution times (WCETs). By reducing our representation of the program's state-space, we reduced the analysis time for the largest program (with 43, 695 reachable states) by a factor of 342, to only 7 seconds.","PeriodicalId":166715,"journal":{"name":"2013 13th International Conference on Application of Concurrency to System Design","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133499202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Parametrised Compositional Verification with Multiple Process and Data Types","authors":"Antti Siirtola, Keijo Heljanko","doi":"10.1109/ACSD.2013.9","DOIUrl":"https://doi.org/10.1109/ACSD.2013.9","url":null,"abstract":"We present an LTS-based (Labelled Transition System) CSP-like (Communicating Sequential Processes) formalism for expressing parametrised systems. The parameters are process types, which determine the number of replicated components, and data types, which enable components with a parametrised state space. We prove that the formalism is compositional and show how to combine two existing results for parametrised verification in order to check trace refinement between parametrised processes. The combined approach gives upper bounds, i.e., cut-offs, for types such that a parametrised verification task collapses into finitely many checks solvable by using existing finite state refinement checking tools. We have implemented the approach and applied it to prove mutual exclusion properties of network protocols and systems with shared resources. To the best our knowledge, our technique is the only one that combines compositionality and completeness with support for multiple parametric process and data types.","PeriodicalId":166715,"journal":{"name":"2013 13th International Conference on Application of Concurrency to System Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122849726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modular Verification of Synchronous Programs","authors":"Manuel Gesell, K. Schneider","doi":"10.1109/ACSD.2013.10","DOIUrl":"https://doi.org/10.1109/ACSD.2013.10","url":null,"abstract":"In this paper, we develop an approach to the modular verification of synchronous programs. To this end, we have to solve two major problems: First, if a synchronous module is verified without its later context, outputs may not be completely determined (since the calling module may add further actions on the outputs of the called module). It is not difficult to see that the open system obtained by modular compilation simulates the closed one obtained by the linker, and therefore, we can preserve all universal temporal properties. Second, a module call may replace the formal input parameters by expressions which corresponds with a substitution of variables in the symbolic transition relation. In particular, this affects the starting point and potential preemption conditions of the module and can therefore dramatically affect the behavior of the module. For this reason, we have to modify the temporal specifications accordingly. We prove a preservation result for this transformation that defines a simulation preorder modulo substitution. Our results finally determine a proof rule for the verification of module calls in imperative synchronous programs.","PeriodicalId":166715,"journal":{"name":"2013 13th International Conference on Application of Concurrency to System Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114911957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Incremental Bisimulation Abstraction Refinement","authors":"Lei Song, Lijun Zhang, H. Hermanns, Jens Chr. Godskesen","doi":"10.1145/2627352","DOIUrl":"https://doi.org/10.1145/2627352","url":null,"abstract":"Abstraction refinement techniques in probabilistic model checking are prominent approaches to the verification of very large or infinite-state probabilistic concurrent systems. At the core of the refinement step lies the implicit or explicit analysis of a counterexample. This paper proposes an abstraction refinement approach for the probabilistic computation tree logic (PCTL), which is based on incrementally computing a sequence of may- and must-quotient automata. These are induced by depth-bounded bisimulation equivalences of increasing depth. The approach is both sound and complete, since the equivalences converge to the genuine PCTL equivalence. Experimental results with a prototype implementation show the effectiveness of the approach.","PeriodicalId":166715,"journal":{"name":"2013 13th International Conference on Application of Concurrency to System Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125281862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}