Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors最新文献_第8页

Design of delay-insensitive three dimension pipeline array multiplier for image processing 用于图像处理的延迟不敏感三维管道阵列乘法器设计

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-01 DOI: 10.1109/ICCD.2002.1106755

A. Taubin, K. Fant, J. McCardle

引用次数: 10

Floating-point fused multiply-add with reduced latency 浮点融合的乘加运算，减少了延迟

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-01 DOI: 10.1109/ICCD.2002.1106762

T. Lang, J. Bruguera

引用次数: 47

Adaptive pipeline depth control for processor power-management 处理器电源管理的自适应管道深度控制

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-01 DOI: 10.1109/ICCD.2002.1106812

A. Efthymiou, J. Garside

引用次数: 54

Don't-care identification on specific bits of test patterns 不要关心测试模式的特定部分的标识

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-01 DOI: 10.1109/ICCD.2002.1106769

K. Miyase, S. Kajihara, I. Pomeranz, S. Reddy

引用次数: 18

A distributed computation platform for wireless embedded sensing 一种无线嵌入式传感分布式计算平台

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-05-05 DOI: 10.1109/ICCD.2002.1106774

A. Savvides, M. Srivastava

引用次数: 83

Efficient PEEC-based inductance extraction using circuit-aware techniques 利用电路感知技术高效的基于peec的电感提取

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1900-01-01 DOI: 10.1109/ICCD.2002.1106808

Haitian Hu, S. Sapatnekar

引用次数: 1

Applying decay strategies to branch predictors for leakage energy savings 将衰减策略应用于分支预测器的泄漏节能

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1900-01-01 DOI: 10.1109/ICCD.2002.1106809

Zhigang Hu, Philo Juang, K. Skadron, D. Clark, M. Martonosi

{"title":"Applying decay strategies to branch predictors for leakage energy savings","authors":"Zhigang Hu, Philo Juang, K. Skadron, D. Clark, M. Martonosi","doi":"10.1109/ICCD.2002.1106809","DOIUrl":"https://doi.org/10.1109/ICCD.2002.1106809","url":null,"abstract":"With technology advancing toward deep submicron, leakage energy is of increasing concern, especially for large onchip array structures such as caches and branch predictors. Recent work has suggested that even larger branch predictors can and should be used in order to improve microprocessor performance. A further consideration is that the branch predictor is a thermal hot spot, thus further increasing its leakage. For these reasons, it is natural to consider applying decay techniques-already shown to reduce leakage energy for caches-to branch-prediction structures. Due to the structural difference between caches and branch predictors, applying decay techniques to branch predictors is not straightforward. This paper explores the strategies for exploiting spatial and temporal locality to make decay effective for bimodal, gshare, and hybrid predictors, as well as the branch target buffer Overall, this paper demonstrates that decay techniques apply more broadly than just to caches, but that careful policy and implementation make the difference between success and failure in building decay-based branch predictors. Multi-component hybrid predictors offer especially interesting implementation tradeoffs for decay.","PeriodicalId":164768,"journal":{"name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128518468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 45

Embedded operating system energy analysis and macro-modeling 嵌入式操作系统能量分析和宏建模

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1900-01-01 DOI: 10.1109/ICCD.2002.1106822

T. K. Tan, A. Raghunathan, N. Jha

{"title":"Embedded operating system energy analysis and macro-modeling","authors":"T. K. Tan, A. Raghunathan, N. Jha","doi":"10.1109/ICCD.2002.1106822","DOIUrl":"https://doi.org/10.1109/ICCD.2002.1106822","url":null,"abstract":"A large and increasing number of modern embedded systems are subject to tight power/energy constraints. It has been demonstrated that the operating system (OS) can have a significant impact on the energy efficiency of the embedded system. Hence, analysis of the energy effects of the OS is of great importance. Conventional approaches to energy analysis of the OS (and embedded software, in general) require the application software to be completely developed and integrated with the system software, and that either measurement on a hardware prototype or detailed simulation of the entire system be performed. Since this process requires significant design effort, unfortunately, it is typically too late in the design cycle to perform high-level or architectural optimizations on the embedded software, restricting the scope of power savings. Our work recognizes the need to provide embedded software designers with feedback about the effect of different OS services on energy consumption early in the design cycle. As a first step in that direction, this paper presents a systematic methodology to perform energy analysis and macro-modeling of an embedded OS. Our energy macro-models provide software architects and developers with an intuitive model for the OS energy effects, since they directly associate energy consumption with OS services and primitives that are visible to the application software. Our methodology consists of (i) an analysis stage, where we identify a set of energy components, called energy characteristics, which are useful to the designer in making OS-related design trade-offs, and (ii) a subsequent macromodeling stage, where we collect data for the identified energy components and automatically derive macro-models for them. We validate our methodology by deriving energy macro-models for two state-of-the-art embedded OS's, /spl mu/C/OS and Linux OS.","PeriodicalId":164768,"journal":{"name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130402375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 40

From ASIC to ASIP: the next design discontinuity 从ASIC到ASIP:下一个设计中断

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1900-01-01 DOI: 10.1109/ICCD.2002.1106752

K. Keutzer, S. Malik, A. Newton

{"title":"From ASIC to ASIP: the next design discontinuity","authors":"K. Keutzer, S. Malik, A. Newton","doi":"10.1109/ICCD.2002.1106752","DOIUrl":"https://doi.org/10.1109/ICCD.2002.1106752","url":null,"abstract":"A variety of factors is making it increasingly difficult and expensive to design and manufacture traditional Application Specific Integrated Circuits (ASICs). This has started a significant move towards the use of programmable solutions of various forms - increasingly referred to as programmable platforms. For the platform manufacturer, programmability provides higher volume to amortize design and manufacturing costs, as the same platform can be used over multiple related applications, as well as over generations of an application. For the application implementer, programmability provides a lower risk and shorter time-to-market implementation path. The flexibility provided by programmability comes with a performance and power overhead. This can be significantly mitigated by using application specific platforms, also referred to as Application Specific Instruction Set Processors (ASIPs). This paper details the reasons for this significant change in application implementation philosophy, provides illustrative contemporary evidence of this change, examines the space of application specific platforms, outlines fundamental problems in their development, and finally presents a methodology to deal with this changing design style.","PeriodicalId":164768,"journal":{"name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133818350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 141

Accelerated SAT-based scheduling of control/data flow graphs 加速基于sat的控制/数据流图调度

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1900-01-01 DOI: 10.1109/ICCD.2002.1106801

S. Memik, F. Fallah

引用次数: 33