2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)最新文献_第3页

Design and Simulation of Peripheral Driving Circuitry for Computational ReRAM 计算型ReRAM外围驱动电路的设计与仿真

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970082

C. Fernandez, I. Vourkas, A. Rubio

{"title":"Design and Simulation of Peripheral Driving Circuitry for Computational ReRAM","authors":"C. Fernandez, I. Vourkas, A. Rubio","doi":"10.1109/DCIS55711.2022.9970082","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970082","url":null,"abstract":"As an alternative approach to the von Neumann architecture, the notion of computational resistive random-access memory (ReRAM) has emerged, promising faster and more energy-efficient computing systems. In this context, we present a classification of ReRAM-compatible logic design strategies and highlight the potential of nonstateful ratioed logic for computational ReRAM modules. We provide insights towards the design of ad-hoc peripheral circuitry that allows the fusion of memory and ratioed logic operations in the ReRAM module in a reliable manner; i.e., the driving/sensing circuitry allows carrying out memory operations and in-memory multilevel ratioed logic operations. To this end, we present in detail a computational ReRAM driver and focus our description on the operational features that enable memory/logic operations in every row of the crossbar array. We validate circuit functionality through LTSpice simulations for read/write memory and logic operations using a threshold-type bipolar ReRAM device model. The presented practical solutions contribute to the viable development of computational ReRAM.","PeriodicalId":163982,"journal":{"name":"2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124395329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays 用多粒可重构覆盖扩展RISC-V处理器数据路径

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970069

Daniel Vázquez, Alfonso Rodríguez, A. Otero, E. D. L. Torre

{"title":"Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays","authors":"Daniel Vázquez, Alfonso Rodríguez, A. Otero, E. D. L. Torre","doi":"10.1109/DCIS55711.2022.9970069","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970069","url":null,"abstract":"The use of accelerators to perform computing offloading from software to hardware in heterogeneous computing systems has already been around for some time. The most common approach is to have hardware accelerators loosely-coupled with the main processor of the system to allow parallel execution. However, this can negatively affect performance in certain application scenarios. A different approach, which is gaining momentum nowadays thanks to the mainstream adoption of RISC-V, is to create accelerators that combine a processor core with dedicated and tightly-coupled hardware modules that are transparently managed via custom ISA extensions. These modules, which are often application-specific, become part of the processor datapath and cannot be changed after deployment. In this paper, a novel reconfigurable RISC-V processor is presented. Its datapath has been modified to include a spatially-configured CGRA overlay that is accessible through custom ISA extensions. The functionality of the overlay can be adapted at run time through reconfiguration. The proposed architecture is accompanied by a toolchain capable of automatically transforming loop-based computing-intensive sections of the application code into configuration data controlling the operations executed in the overlay. Experimental results show a performance improvement of up to 13x compared to alternative software-based and memory-mapped hardware-based implementations.","PeriodicalId":163982,"journal":{"name":"2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122721948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hierarchical Modeling of 868MHz Wake-up Radio in OMNeT++ omnet++中868MHz唤醒无线电的分层建模

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970153

Ruochen Ding, W. Tatinian

引用次数: 1

Design and development of an IoT device provided with a voice interface to improve treatment adherence in polymedicated patients 设计和开发具有语音接口的物联网设备，以提高多药患者的治疗依从性

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970156

José Luis Unibaso, J. Araujo, Jesús Lázaro, J. Jiménez, Leire Muguira

引用次数: 0

Analysis and methodology for enabling DNN inference in an IoT edge environment in depth completion tasks 在深度完成任务的物联网边缘环境中启用DNN推理的分析和方法

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970054

Alejandro Martinez de Ternero, Jaime Sancho, Guillermo Vázquez, M. Villa, Gonzalo Rosa, Pallabi Sutradhar, A. Martín-Pérez, M. Chavarrías, L. Jimenez-Roldan, Á. Pérez-Núñez, Alfonso Lagares, E. Juárez, C. Sanz

{"title":"Analysis and methodology for enabling DNN inference in an IoT edge environment in depth completion tasks","authors":"Alejandro Martinez de Ternero, Jaime Sancho, Guillermo Vázquez, M. Villa, Gonzalo Rosa, Pallabi Sutradhar, A. Martín-Pérez, M. Chavarrías, L. Jimenez-Roldan, Á. Pérez-Núñez, Alfonso Lagares, E. Juárez, C. Sanz","doi":"10.1109/DCIS55711.2022.9970054","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970054","url":null,"abstract":"IoT and artificial intelligence (AI) have attracted a huge amount of interest in recent years, creating the so-called edge artificial intelligence field. However, due to the tendency in AI to create larger and more complex models, these algorithms are often not suitable for resource-restricted devices, and efforts have to be made in the direction of optimizing AI for IoT. This paper presents an analysis of three different tools that allow the use of Deep Neural Network (DNN) models in resource-limited devices: (i) a deep neural network compressor, (ii) the use of different bit-precision operations in the model, and (iii) the use of a specific accelerator engine in the constrained device. For that purpose, an IoT architecture is followed in which the edge device is a constrained device which takes the model pre-trained from the cloud and performs real-time inference. In particular, four common CNN building blocks have been compared in an encoder-decoder architecture, in order to improve the depth maps generated by LiDAR-like cameras in situ. The resulting architectures have been analyzed in terms of quality, energy consumption and inference time, measuring the effects of the compressor, the bit precision and the accelerator engine. The results obtained show that the use of a methodology based on these three tools combined is beneficial to reduce the size of the model more than ×8 times, energy consumption by almost ×3 times, and an increase in speed by ×3 times from the base model, without compromising the quality of the model.","PeriodicalId":163982,"journal":{"name":"2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125862617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhancing Storage Capabilities of Oscillatory Neural Networks as Associative Memory 增强振荡神经网络作为联想记忆的存储能力

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970122

M. Jiménèz, M. Avedillo, J. Núñez, B. Linares-Barranco

引用次数: 1

Load Optimized Gate Driving for Charge Pumps 电荷泵负载优化栅驱动

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970011

Carlos Santos, Jorge R. Fernandes, Marcelino Santos

引用次数: 0

SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate SerOpt:晶体管尺寸算法和优化实用程序，以尽量减少软错误率

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970146

Yehuda Kra, Y. Weizman, A. Teman

引用次数: 0

Accelerating Video Analytic Processing on Edge Intelligence 基于边缘智能的加速视频分析处理

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970152

P. Fernandez, J. Jiménez, A. Astarloa, Mikel Idirin, Sergio Salas

引用次数: 0

Low-Power CMOS Amplifiers for Wideband Impedance Spectroscopy Applications 用于宽带阻抗谱应用的低功耗CMOS放大器

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970024

J. Pérez-Bailón, B. Calvo, N. Medrano

引用次数: 0