2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)最新文献_第2页

An Extreme Edge Low Power Device with Wavelet-based Compression for Physiological signals 一种基于小波压缩生理信号的极边缘低功耗器件

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970154

L. Gutiérrez-Martín, M.J. Sánchez Naranjo, J. A. Miranda Calero, C. López-Ongil

引用次数: 0

High power and high bandwidth CMOS driver for hybrid interconnected GaN microdisplay 用于混合互联GaN微显示器的高功率高带宽CMOS驱动器

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970019

V. Moro, N. Franch, J. Canals, J. Prades, G. Schöttler, S. Bornemann, A. Waag, Á. Diéguez

引用次数: 0

Hardware implementation of self-organizing maps using memristors, a simulation study 用忆阻器实现自组织地图的硬件实现，仿真研究

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970139

Germán Vaquero, F. Jiménez-Molinos, J. Roldán

引用次数: 0

On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data 基于TiN/Ti/HfO2/W实验数据的RRAM斯坦福模型参数拟合与改进

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970051

V. Mahboubi, D. Arumí, A. Gómez, R. Rodríguez, S. Manich

引用次数: 0

Data Synchronization in Non-Uniform Latency Custom DSP Designs 非均匀延迟自定义DSP设计中的数据同步

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970167

Samuel López Asunción, P. Ituero, M. López-Vallejo, J. Grajal

{"title":"Data Synchronization in Non-Uniform Latency Custom DSP Designs","authors":"Samuel López Asunción, P. Ituero, M. López-Vallejo, J. Grajal","doi":"10.1109/DCIS55711.2022.9970167","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970167","url":null,"abstract":"Many DSP algorithms for streams of constant-sample-rate data work by processing the signal by pieces, splitting the input signal into fixed-length blocks in order to calculate some parameter related to that chunk of signal. In custom multiblock DSP architectures, this kind of operations are laid out to be carried out in parallel. This poses a challenge since these operations may have greatly different latency values, so the data needs to be synchronized somehow for the following DSP block to acknowledge the results of the operations and keep on with the computation. In our proposal, we monitor the operations in order to synchronize the output data by storing the results until all operations are done. Every output is queued up in a FIFO structure so that when all the operations are complete the results can then be transferred to the next module simultaneously. The control structure is built so that the architecture also works when the signal blocks have variable length, or when the operations have variable latency. This approach allows for a reduction in the number of registers needed for a delay chain implementation, it is more flexible if the latency of the operations change, and can be easily updated if new operations are introduced. This architecture has been used and extensively tested in an Automatic Modulation Classifier implementation on an FPGA as part of a signal processing chain with parallel calculations of linear regressions and central moments of a constant-rate signal divided into blocks of different lengths.","PeriodicalId":163982,"journal":{"name":"2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129881970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A lossless compression solution for SCIP and TuMag instruments aboard of SUNRISE III balloon-borne Solar Observatory 一个无损压缩解决方案的SCIP和TuMag仪器上的SUNRISE III气球载太阳天文台

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970132

Antonio J. Sánchez, Y. Barrios, R. Sarmiento, D. H. Expósito, A. S. Gómez

引用次数: 1

SRAM-cells Reproducibility Metrics for Physical Unclonable Function Applications 物理不可克隆功能应用的sram细胞再现性度量

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970171

A. Alheyasat, G. Torrens, S. Bota, B. Alorda

引用次数: 0

Customizing the CVA6 RISC-V Core to Integrate Posit and Quire Instructions 定制CVA6 RISC-V核心以集成Posit和Quire指令

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970026

David Mallasén, Raul Murillo, A. D. Del Barrio, G. Botella, L. Piñuel, Manuel Prieto-Matias

{"title":"Customizing the CVA6 RISC-V Core to Integrate Posit and Quire Instructions","authors":"David Mallasén, Raul Murillo, A. D. Del Barrio, G. Botella, L. Piñuel, Manuel Prieto-Matias","doi":"10.1109/DCIS55711.2022.9970026","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970026","url":null,"abstract":"The posit representation for real numbers, aka Unum-v3, is an alternative to substitute the IEEE 754 standard and thus mitigate the inherent problems to the construction of floating-point numbers. Nonetheless, posits are not standard yet, and previously there was no approach, neither academically nor industrially, which implemented a fully compliant core for deploying this novel format. Recently, the open-source PERCIVAL posit RISC-V core was presented as the first work that fully integrates posit arithmetic and quire capabilities into hardware. In addition, Xposit, a RISC-V extension for posit operations allows for the compilation of C programs with inline assembly posit and quire instructions. As a study platform, PERCIVAL is based on the CVA6 core and has support for both posit and IEEE 754 formats, further permitting the comparison of these representations. This paper details the microarchitecture of the Posit Arithmetic Unit with quire added to this core. It also describes how to perform the necessary additions and modifications to the CVA6 core to add support for the Xposit RISC-V custom extension. Furthermore, FPGA synthesis results highlight the cost of including support for both posits with quire and IEEE 754 formats. This is done by breaking down the area resources needed for every arithmetic configuration.","PeriodicalId":163982,"journal":{"name":"2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124009127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Improving efficiency of a Stochastic Computing-based Morphological Neural Network 提高随机计算形态神经网络的效率

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970034

E. S. Skibinsky-Gitlin, J. Font-Rosselló, Christiam F. Frasser, Alejandro Morán, Vicens Canals, M. Roca, J. Rosselló

引用次数: 0

Asynchronous Controller Design and Simulation Using Signal Transition Graphs 基于信号转换图的异步控制器设计与仿真

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS) Pub Date : 2022-11-16 DOI: 10.1109/DCIS55711.2022.9970038

Diogo C. P. Domingos, Marcelino Santos

引用次数: 0