{"title":"Simulated Leakage Power Analysis Attack of the Trivium Stream Cipher","authors":"Kenneth Palma, F. Moll","doi":"10.1109/DCIS55711.2022.9970061","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970061","url":null,"abstract":"In this paper, the theoretical basis for power analysis attacks on the Trivium utilizing leakage current as a side-channel are presented. The analysis is first established in the case of an ideal implementation without the presence of algorithmic noise, and goes on to examine the potential sources of algorithmic noise present in the system, deriving worst case scenario figures of the Pearson Correlation Coefficient (PCC). The same analysis is then performed under the presence of FDSOI random body bias countermeasures. The theoretical analysis are contrasted with simulations of the Trivium cipher under the assumption of a noiseless side-channel, showcasing the theoretical feasibility of utilizing leakage current as a means to attack the cryptosytem.","PeriodicalId":163982,"journal":{"name":"2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123830025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. R. Sparrow, S. Bourdel, G. Jacquemod, J. Gaubert
{"title":"A 6.3 pJ/b Ultra-low Power Energy Detector for Non-Coherent UWB Impulse Radio Receiver","authors":"O. R. Sparrow, S. Bourdel, G. Jacquemod, J. Gaubert","doi":"10.1109/DCIS55711.2022.9970057","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970057","url":null,"abstract":"This paper presents a 130nm CMOS (HCMOS9 from ST-Microelectronics) 6.3 pJ/b ultra-low power energy detector circuit design and implementation. The designed energy detector is implemented with three blocks: the squarer based on a MOS transistor biased in the subthreshold region, the integrator based on a low pass amplifier and a decision circuit. The energy detector is driven by a LNA of 30 dB gain. The experimental results show that a BER of 10–3 is achieved for a peak to peak voltage of 3.4 mV at receiver input for a data rate of 100 Mb/s, leading to a receiver sensitivity of -58.4 dBm. The energy power consumption is 0.63 mW resulting in an energy of 6.3 pJ/b. The overall Rx power consumption is 14.4 mW (100 % duty cycled) with a 1.2 V supply voltage when the receiver is always on. This value is drastically reduced with a power gating technique due to the duty cycle of the IR-UWB pulses. For example, assuming an on-stage window of 5 ns, the total power consumption becomes 7.2 mW @ 100 Mb/s. The chip area is 1.43 mm2.","PeriodicalId":163982,"journal":{"name":"2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116269242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pallabi Sutradhar, Jaime Sancho, M. Villa, A. Martín-Pérez, Guillermo Vázquez, Gonzalo Rosa, Alejandro Martinez de Ternero, L. Jimenez-Roldan, Á. Pérez-Núñez, Alfonso Lagares, M. Chavarrías, E. Juárez, C. Sanz
{"title":"Exploration of Realtime Brain tumor classification from Hyperspectral Images in Heterogeneous Embedded MPSoC","authors":"Pallabi Sutradhar, Jaime Sancho, M. Villa, A. Martín-Pérez, Guillermo Vázquez, Gonzalo Rosa, Alejandro Martinez de Ternero, L. Jimenez-Roldan, Á. Pérez-Núñez, Alfonso Lagares, M. Chavarrías, E. Juárez, C. Sanz","doi":"10.1109/DCIS55711.2022.9970064","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970064","url":null,"abstract":"With the growth in the complexity of image processing algorithms, the computational power of processing systems must keep up with the requirements. To respond to ubiquitous, spatial or energy constrained environments, developers turn to specific embedded systems. In this work, a multiprocessor system-on-chip (MPSoC) ZCU102 Evaluation Kit from the Xilinx Zynq Ultrascale+ family is used for hyperspectral (HS) image processing dedicated to real-time classification of brain tissue. Another main objective of this work is to analyze and compare the performance of realtime HS image classification between different embedded platforms. To the best of our knowledge, this has not been done before in any MPSoC environment of this type. In this case, four processing elements (PE) present in the MPSoC have been used and the ARM Cortex-A53 processor and a high-end FPGA have been selected for experimentation. The ARM processor is used to govern the acquisition of high speed image frames and the implementation of the complete chain of the classification process. The full classification process takes around 586 ms to classify an HS image frame. The spectral correction processing block represents 40% of the total processing time. Next, the possible speed-up of the spectral correction with the FPGA is explored and it is found that the speed-up is more than 5 times faster than the time taken by the ARM processor. Therefore, it can be concluded that the ZCU102 FPGA is a potential candidate for further implementation and experimentation of the HS image classification process chain.","PeriodicalId":163982,"journal":{"name":"2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)","volume":"44 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120839446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Iñigo Mikel Lasaga Arana, A. Ramírez-Bárcenas, M. García-Valderas, C. López-Ongil
{"title":"Low Power Consumption Online Testing Technique for Wearable Wireless Body Area Networks","authors":"Iñigo Mikel Lasaga Arana, A. Ramírez-Bárcenas, M. García-Valderas, C. López-Ongil","doi":"10.1109/DCIS55711.2022.9970190","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970190","url":null,"abstract":"Internet of Things (IoT) is a growing field of research and in real-life applications. Cyber-physical Systems are aimed to monitor physical variables, processing data, applying artificial intelligent algorithms, and responding in real time for further actions. For example, on-the-edge medical monitoring of chronic illnesses or supervising of an industrial process can help to early detect small anomalies or misfunctions, preventing catastrophic events or assuring minimum quality thresholds. These systems require continuous monitoring, data collection, signal processing and analysis, which demand smart sensors, efficient wireless communications, and powerful processing modules. This is especially critical in wearable body area networks (BAN) where size, weight and power consumption are key elements in the system's usability and attractiveness. Dependability becomes a big concern in the design and deployment of wearable devices that can be considered unsupervised wireless nodes, with high complexity in architecture and functionality. This work proposes the integration of a software online testing procedure for monitoring intra-node faults appearance, detecting the presence of errors, reporting their effects, and performing a graceful degradation when possible, maintaining a low power consumption. The online testing proposal has been implemented and validated in a real system, Bindi from the UC3M4Safety team. The effect on the power consumption has been measured showing a very low effect on the overall power budget.","PeriodicalId":163982,"journal":{"name":"2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125819013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Gogolou, Konstantinos Kozalakis, T. Laopoulos, S. Siskos
{"title":"A Triboelectric Energy Harvesting Autonomous System for Internet-of-Things Applications","authors":"V. Gogolou, Konstantinos Kozalakis, T. Laopoulos, S. Siskos","doi":"10.1109/DCIS55711.2022.9970196","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970196","url":null,"abstract":"In this work, an autonomous system, based on triboelectric energy harvesting is presented. The system consists of a rotary triboelectric generator (TEG), a DMOS full-wave rectifier and a buck DC-DC converter based on a silicon-controlled rectifier (SCR) switch. An ultra-low-power low-complexity output voltage regulation control is implemented in order to efficiently manage the harnessed energy and simultaneously provide regulated voltage to the connected loads. To minimize the power losses, the DMOS full-wave rectifier as well as the output voltage regulation control are implemented on a 0.18μm CMOS process. The rectifier is implemented using floating gate DMOS transistors in order to sustain large input voltages at the transistors' gate terminals. The SCR-based buck DC-DC converter is implemented with discrete components. The total power consumption is measured at 216nA at 2.25V. The overall system presents autonomous operation and does not require external power supply. The experimental results validate the proper operation of the proposed system.","PeriodicalId":163982,"journal":{"name":"2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127363253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"BTI-Aware Cell Characterization based on Neural Network","authors":"Seok-Jun Kim, M. Choi, Juho Kim","doi":"10.1109/DCIS55711.2022.9970108","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970108","url":null,"abstract":"As semiconductor technology scales down, Bias Temperature instability (BTI) became more important in the presence of reliability of CMOS circuits. Also scaling down of the circuits has more effect on the performance due to the aging effect, leading to an increase in time complexity for cell characterization. In this paper, to cope with the time complexity issues, we propose neural network based cell characterization considering BTI to predict gate delay faster and accurately. Our proposed method extracts the delay time of gates with HSPICE simulation to use as training data for the neural network. The model generated after training with the neural network can predict the gate delay of specific conditions. Experiment results show that our model can reduce cell characterization time 700x faster compared to HSPICE with 98.15% accuracy.","PeriodicalId":163982,"journal":{"name":"2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123292465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. S. Gracia, A. Valero, Rubén Gran Tejero, M. Villarroya-Gaudó, V. Viñals
{"title":"peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter","authors":"D. S. Gracia, A. Valero, Rubén Gran Tejero, M. Villarroya-Gaudó, V. Viñals","doi":"10.1109/DCIS55711.2022.9970050","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970050","url":null,"abstract":"The fast advances of computer systems translate into a growing demand of methodologies and tools to introduce those novelties into classes. Among the plethora of those advances, virtualization has become an essential technology in almost every relevant system stack, from connected cars to hyperscaled cloud servers. However, introducing those technologies into the classroom remains a challenging task because of the huge complexity of their software components that may hinder the learning process of students. peRISCVcope aims to help in this area by proposing a tiny yet powerful interpreter to dig into virtualization technologies, such as the implementation of trap&emulate hypervisors. With less than 2,000 lines of code, and thanks to the conciseness of the RV32I base instruction set of RISC-V, peRISCVcope enables students to make virtualization knowledge their own. This paper presents our experiences developing and testing a virtualization laboratory where students implement parts of an interpreter. After the practical experience, peRISCVcope has been proved as a useful pedagogical tool, and, most importantly, students have positively rated the experience.","PeriodicalId":163982,"journal":{"name":"2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122564956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Alba Páez-Montoro, J. A. M. Calero, Juan Marcos–Torero, C. López-Ongil
{"title":"Towards a Smart Earring for Continuous Heart Rate and Audio Monitoring","authors":"Alba Páez-Montoro, J. A. M. Calero, Juan Marcos–Torero, C. López-Ongil","doi":"10.1109/DCIS55711.2022.9970091","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970091","url":null,"abstract":"The use of smart wearable devices has increased in fields like healthcare or activity tracking in the past few years. However, the conceptualization, design, and integration of multimodal wearable systems needs to be further developed and boosted. Besides being comfortable and discrete, smart wearables need to consider the acquisition of different modalities or sources of information to cope and tackle with upcoming challenges to be performed within the edge-computing context. On this basis, this work proposes a new smart device that includes multimodal acquisition and processing capabilities. Specifically, a smart earring was designed. It consists of a heart rate sensor and two microphones. The objective of this work is twofold, to compare the different microphone technologies integrated within the device, and to test the heart rate measuring viability in the earlobe. Results reported that piezoelectric microphones are a better option since they are hermetic and have a better frequency response when sealed. Moreover, it was proven that heart rate can be successfully measured in the earlobe. This research is intended as a step towards a multimodal and inconspicuous smart device design, which facilitates further work with the development of novel wearable systems and with real-life data acquisition.","PeriodicalId":163982,"journal":{"name":"2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132340613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"10 mA Precision Contactless Current Sensing Using Low-Cost Hall-Effect Devices","authors":"N. Medrano, D. Antolín, B. Calvo, Daniel Enériz","doi":"10.1109/DCIS55711.2022.9970200","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970200","url":null,"abstract":"The measurement of the magnetic field generated by a current flowing in a wire allows the contactless estimation of its value. This non-invasive measurement technique can be applied to occasional monitoring of energy consumption in electrical and electronic systems. In this paper, based on low-cost linear Hall-effect sensors, a basic circuit for AC and DC current sensing is presented targeting current ranges of home and automotive applications. With an accuracy of 10 mA, the probe prototype consists of a differential configuration with programmable gain, so that the output voltage can be dynamically set to cover the input range of an analog-to-digital converter.","PeriodicalId":163982,"journal":{"name":"2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134156515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Santiago, Leire Muguira, J. Jiménez, Le Sun, Jesús Lázaro
{"title":"Analysis and Deployment of Applications Acceleration Environment for Xilinx Hardware-Accelerated Platforms","authors":"A. Santiago, Leire Muguira, J. Jiménez, Le Sun, Jesús Lázaro","doi":"10.1109/DCIS55711.2022.9970101","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970101","url":null,"abstract":"High Performance Computing is a practice that consists of adding computing power above what any typical computer or workstation can provide. Greater performance is achieved by solving complex problems. The aim is to obtain a more efficient, reliable, and faster processing than traditional methods. The foundation of this technology is based on the parallelization of the processing units so that a higher performance per unit of time is achieved. This can be get with highperformance hardware or by combining simpler hardware, giving rise to clusters or supercomputers, depending on the form of grouping. Once the general acceleration process of an application and the methodology on which it is based have been understood, a complete analysis of the performance of a specific algorithm or program has been carried out and implemented using different programming languages and technologies. Besides, a series of conclusions and results related to the acceleration of applications through acceleration hardware have been obtained, determining its potential and the possible inconveniences it entails.","PeriodicalId":163982,"journal":{"name":"2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115837988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}