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2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)最新文献

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Design of a LDO Circuit Based on RFID Technology 基于RFID技术的LDO电路设计
2021 IEEE 3rd International Conference on Circuits and Systems (ICCS) Pub Date : 2021-10-29 DOI: 10.1109/ICCS52645.2021.9697199
Qiao Li, Yong Xu, Qinglong Li, Xian Zhang
{"title":"Design of a LDO Circuit Based on RFID Technology","authors":"Qiao Li, Yong Xu, Qinglong Li, Xian Zhang","doi":"10.1109/ICCS52645.2021.9697199","DOIUrl":"https://doi.org/10.1109/ICCS52645.2021.9697199","url":null,"abstract":"This paper introduces a design of LDO (low dropout regulator) circuit based on RFID (Radio frequency identification) technology. It consists of rectifier circuit, bandgap reference circuit and LDO circuit. The rectifier circuit receives and processes the signals sent by the antenna. The bandgap reference circuit generates a reference voltage. LDO circuit outputs a stable voltage. The circuit based on 0.18 μm CMOS process outputs a stable voltage of 1.8V.","PeriodicalId":163200,"journal":{"name":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115991940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
New Single-Phase Bridgeless High-Voltage-Gain SEPIC PFC Converters with Improved Efficiency 高效率的新型单相无桥高压增益SEPIC PFC变换器
2021 IEEE 3rd International Conference on Circuits and Systems (ICCS) Pub Date : 2021-10-29 DOI: 10.1109/ICCS52645.2021.9697323
Xiang Lin, J. Luo, Shumin Ding
{"title":"New Single-Phase Bridgeless High-Voltage-Gain SEPIC PFC Converters with Improved Efficiency","authors":"Xiang Lin, J. Luo, Shumin Ding","doi":"10.1109/ICCS52645.2021.9697323","DOIUrl":"https://doi.org/10.1109/ICCS52645.2021.9697323","url":null,"abstract":"Bridgeless power factor correction circuits are creditable for its merit of reducing conduction losses in semiconductors. In this paper, three new bridgeless single ended primary inductor converter (SEPIC) PFC converters by adopting switched-capacitor (SC) cell are proposed. Owing to the inbuilt SC cell, higher voltage gain can be generated than conventional SEPIC PFC converter. Compared to its conventional full-bridge counterparts, the proposed bridgeless SEPIC PFC converters feature a reduced conduction losses in semiconductors under the same operation parameters, contributing to improved efficiency. Furthermore, the proposed bridgeless SEPIC PFC converters adopt simple circuit structure. In addition, the proposed bridgeless SEPIC PFC converters are designed in discontinuous conduction mode (DCM) with the merits of inherently current-sharping capability and zero-current switching in semiconductors. The simulation results are provided in order to verify superiority of the proposed bridgeless SEPIC PFC converters.","PeriodicalId":163200,"journal":{"name":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128314121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a Digital Decimation Filter with High Speed and Low Complexity 一种高速低复杂度数字抽取滤波器的设计
2021 IEEE 3rd International Conference on Circuits and Systems (ICCS) Pub Date : 2021-10-29 DOI: 10.1109/ICCS52645.2021.9697215
Xiaochen Li, Ying Shang, Ruilian Zhao, Beili Jiang
{"title":"Design of a Digital Decimation Filter with High Speed and Low Complexity","authors":"Xiaochen Li, Ying Shang, Ruilian Zhao, Beili Jiang","doi":"10.1109/ICCS52645.2021.9697215","DOIUrl":"https://doi.org/10.1109/ICCS52645.2021.9697215","url":null,"abstract":"Digital filter is an important component of analog-to-digital converter. The speed and complexity of digital decimation filter have a great influence on Sigma Delta analog-to-digital converter. In view of this situation, a design of high speed and low complexity digital filter is presented in this paper. A three stages cascaded architecture is adopted to reduce the number of half-band filters by increasing the downsampling rate of cascaded integrator-comb filter. The cascaded integrator-comb filter adopts a serial-parallel mixed structure to improve the speed of data processing. In order to reduce the complexity of digital filter, a novel sine compensation filter is proposed to compensate the passband attenuation and the multipliers of half-band filter are designed by time division multiplexing technique. The simulation results and analysis show that this design meets the performance requirements and its speed is increased by four times. Compared with the same type of filters, the number of multipliers, adders and registers has decreased by 45%, 31% and 26% respectively.","PeriodicalId":163200,"journal":{"name":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132935948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis and Design of Sigma-Delta ADCs for Automotive Control Systems 汽车控制系统中Sigma-Delta数模转换器的分析与设计
2021 IEEE 3rd International Conference on Circuits and Systems (ICCS) Pub Date : 2021-10-29 DOI: 10.1109/ICCS52645.2021.9697210
Yushi Chen, Zhiyuan Wang, Y. Zhuang, Hualian Tang
{"title":"Analysis and Design of Sigma-Delta ADCs for Automotive Control Systems","authors":"Yushi Chen, Zhiyuan Wang, Y. Zhuang, Hualian Tang","doi":"10.1109/ICCS52645.2021.9697210","DOIUrl":"https://doi.org/10.1109/ICCS52645.2021.9697210","url":null,"abstract":"This paper presents a sigma-delta analog-to-digital converter (ADC) using discrete-time implementation dedicated to automotive control systems. The proposed ADC consists of a fourth-order sigma-delta modulator followed by a fifth-order cascaded integrator comb (CIC) decimator filter. The structure of the proposed modulator employs a cascaded integrator feed-forward (CIFF) topology. By using multi-bit quantizer, the modulator can apparently reduce quantization noise and make the loop more stable. Thanks to the input offset storage (IOS) technology and neutralization technology, the offset voltage of the comparator is sharply reduced by 35.5% and kick back noise is also eliminated. A random digital correction method is applied to make the feedback DAC insensitive to the mismatch of small-size capacitors and achieve better dynamic performance. The proposed ADC is implemented in a standard 0.18um CMOS process. Operating from a 1.8V supply, it achieves a peak spurious-free dynamic range (SFDR) of 105.8 dB and a peak signal-to-noise and distortion ratio (SNDR) of 93 dB at a conversion rate of 1 MS/s. The power consumption is 8.28 mW, which corresponds to a Walden figure-of-merit of 7.2 pJ/conv and a Schreier figure-of-merit of 155.8 dB.","PeriodicalId":163200,"journal":{"name":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","volume":"329 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134553993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Quality Assessment System for PPG Waveform 一种PPG波形质量评估系统
2021 IEEE 3rd International Conference on Circuits and Systems (ICCS) Pub Date : 2021-10-29 DOI: 10.1109/ICCS52645.2021.9697132
Jiang Hao, Gao Bo
{"title":"A Quality Assessment System for PPG Waveform","authors":"Jiang Hao, Gao Bo","doi":"10.1109/ICCS52645.2021.9697132","DOIUrl":"https://doi.org/10.1109/ICCS52645.2021.9697132","url":null,"abstract":"The paper presents a quality assessment system for the PPG waveform considering different noise conditions to reduce monitoring errors. The proposed algorithm adopts the hierarchical decision rules combining the absolute value of amplitude, zero-crossing threshold, and autocorrelation function characteristics. During assessment for 1782 unacceptable PPG waveform segments and 17918 acceptable PPG waveform segments, the algorithm achieves a sensitivity of 99.94%, a specificity of 99.39%, and an accuracy rate of 99.89%.","PeriodicalId":163200,"journal":{"name":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134432828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Rapid Evaluation Technology for SEU in Convolutional Neural Network Circuits 卷积神经网络电路中SEU的快速评估技术
2021 IEEE 3rd International Conference on Circuits and Systems (ICCS) Pub Date : 2021-10-29 DOI: 10.1109/ICCS52645.2021.9697197
Kai Chen, Xin Chen, Ying Zhang, Zhiwei Zhang
{"title":"A Rapid Evaluation Technology for SEU in Convolutional Neural Network Circuits","authors":"Kai Chen, Xin Chen, Ying Zhang, Zhiwei Zhang","doi":"10.1109/ICCS52645.2021.9697197","DOIUrl":"https://doi.org/10.1109/ICCS52645.2021.9697197","url":null,"abstract":"This paper proposes a rapid Single Event Upset (SEU) evaluation platform that can perform fault injection at the algorithm level in Convolutional Neural Network (CNN), which is designed by software and hardware co-design. This proposed platform analyzes the layer structure and input parameters of CNN, generates the corresponding fault list and then performs fault injection at the algorithm-level in software side and mapped to the registers of hardware acceleration. Finally, the operation results of CNN after fault injection is analyzed to evaluate the robustness of CNN against SEU, and identify the sensitive areas of SEU. In this paper, SEU fault injection experiments are carried out on YOLOv2 neural network. Experimental results show that fault injection and sensitivity evaluation based on this method can analyze the overall robustness of CNN against SEU quickly and effectively. From the analysis of experimental results, the algorithmic nodes which are sensitive to SEU are located, and the efficiency of this rapid evaluation technology is also verified.","PeriodicalId":163200,"journal":{"name":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130551376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A High Frequency Stability Feedback Lock On-chip Oscillator 一种高频稳定反馈锁片振荡器
2021 IEEE 3rd International Conference on Circuits and Systems (ICCS) Pub Date : 2021-10-29 DOI: 10.1109/ICCS52645.2021.9697198
Chenrui Wu, Yin Zhang, Junyue Tao, Anbang Sun, Zhendong Cai, Meilin Wan
{"title":"A High Frequency Stability Feedback Lock On-chip Oscillator","authors":"Chenrui Wu, Yin Zhang, Junyue Tao, Anbang Sun, Zhendong Cai, Meilin Wan","doi":"10.1109/ICCS52645.2021.9697198","DOIUrl":"https://doi.org/10.1109/ICCS52645.2021.9697198","url":null,"abstract":"A feedback loop frequency lock on-chip oscillator (FLO) is proposed to provide an accurate and stable clock. The circuit will operate in three steps successively to charge sense capacitor, compare and change the difference between the voltage of sense capacitor and reference voltage into the alternation of VCO oscillation frequency, and discharge sense capacitor circularly. The above three steps will be repeated and the operating frequency of the VCO will be locked in the state that the charged voltage of sense capacitor is equal to the reference voltage VREF. Since the comparation between the voltage of sense capacitor and reference voltage is realized in one cycle of VCO’s output clock, the delay of comparator will not introduce random clock deviation and the circuit can achieve a more stable on chip clock. The proposed feedback loop frequency lock on-chip oscillator is designed using a 0.18 μm standard CMOS process, and the simulation results show that the frequency deviation is less than 0.6% in the temperature range of −40 – 125 °C when the oscillation of VCO is 525 KHz.","PeriodicalId":163200,"journal":{"name":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125793844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Studies on the Phase Characteristic of S-band RKA: Reducing RF Phase Jitter by Reducing Intense Pulse Fluctuation s波段RKA相位特性研究:通过减小强脉冲波动来减小射频相位抖动
2021 IEEE 3rd International Conference on Circuits and Systems (ICCS) Pub Date : 2021-10-29 DOI: 10.1109/ICCS52645.2021.9697112
Xixi Feng, Yi Ge, Huang Yuan, Hua Huang, Zhenbang Liu
{"title":"Studies on the Phase Characteristic of S-band RKA: Reducing RF Phase Jitter by Reducing Intense Pulse Fluctuation","authors":"Xixi Feng, Yi Ge, Huang Yuan, Hua Huang, Zhenbang Liu","doi":"10.1109/ICCS52645.2021.9697112","DOIUrl":"https://doi.org/10.1109/ICCS52645.2021.9697112","url":null,"abstract":"The phase characteristic is an important parameter of the intense relativistic klystron amplifier (RKA). But the intense pulse voltage produced by high-power pulse power source exists inherent fluctuations, which will affect the RF phase stability of RKA’s output microwave. In this paper, the one-dimensional nonlinearity theory is used to analysis the influences of electron beam voltage jitter on S-band RKA’s phase characteristic under different cavity parameters. Then the PIC simulations are performed to verify the theoretical results. By optimizing the structure parameters of cavities, the RF phase jitter caused by pulse voltage fluctuations is reduced effectively with experimental confirmation. The results suggest that the RF phase jitter caused by voltage fluctuations can be reduced effectively by optimizing the cavity parameters, especially the frequency of mid-cavity and output-cavity, and the Q value of output-cavity. By comprehensive optimizing cavity parameters, the phase jitter can be reduced by 30% while keeping the output power reduced within 15%. The results provide important guidance for improving the RKA phase stability.","PeriodicalId":163200,"journal":{"name":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115359734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Rejection of Periodic Disturbances with Unknown Dominating Frequencies for a Class of Nonlinear Circuit Systems 一类非线性电路系统对未知支配频率周期扰动的抑制
2021 IEEE 3rd International Conference on Circuits and Systems (ICCS) Pub Date : 2021-10-29 DOI: 10.1109/ICCS52645.2021.9697311
Shuping Guo, He Cai
{"title":"Rejection of Periodic Disturbances with Unknown Dominating Frequencies for a Class of Nonlinear Circuit Systems","authors":"Shuping Guo, He Cai","doi":"10.1109/ICCS52645.2021.9697311","DOIUrl":"https://doi.org/10.1109/ICCS52645.2021.9697311","url":null,"abstract":"In this paper, we consider the disturbance rejection problem for a class of nonlinear circuit systems. It is assumed that the disturbance is periodic with dominating frequencies. Specifically, by Fourier expansion, the periodic disturbance consists of two parts, namely, the dominating part and the residual part. The former one is made up of a constant bias and finitely many sinusoidal components with large amplitudes, while the latter one comprises infinitely many sinusoidal components with comparatively small amplitude. It is proved that, by integrating the sliding mode control approach with adaptive internal model technique, the dominating gain of the sliding mode controller can be further reduced, which would suppress the amplitude of the magnitude of control input chatting.","PeriodicalId":163200,"journal":{"name":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130999593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Precise Analog Multiplication Circuit Module for the Pressure Sensor’s Linearization 用于压力传感器线性化的精确模拟倍增电路模块
2021 IEEE 3rd International Conference on Circuits and Systems (ICCS) Pub Date : 2021-10-29 DOI: 10.1109/ICCS52645.2021.9697233
Jing Kai, Zhao Dongmin, Jia Yangpeng, Yu Ningmei
{"title":"A Precise Analog Multiplication Circuit Module for the Pressure Sensor’s Linearization","authors":"Jing Kai, Zhao Dongmin, Jia Yangpeng, Yu Ningmei","doi":"10.1109/ICCS52645.2021.9697233","DOIUrl":"https://doi.org/10.1109/ICCS52645.2021.9697233","url":null,"abstract":"In this paper, an 8-bit current-steering digital-to-analog converter for pressure sensor’s analog linearization is proposed. The circuit adopts a 7bit-Sign segmented structure and is built on Cadence. The lower four bits are coded by binary, the higher three bits are coded by unary, and the sign bit is used to control the rise and fall of the steps to complete the function of the 8-bit DAC, which greatly reduces the layout area and improves the circuit accuracy. The circuit mainly includes a decoding circuit, unit current cells and switches, high-gain operational amplifier and sign bit circuit. Finally, the dynamic and static characteristics of this DAC are calculated, where differential nonlinearity(DNL) is 0 LSB, integral nonlinearity (INL) is less than 0.1 LSB and spurious-free dynamic range (SFDR) is 52dB.","PeriodicalId":163200,"journal":{"name":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126243533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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