A High Frequency Stability Feedback Lock On-chip Oscillator

Abstract

A feedback loop frequency lock on-chip oscillator (FLO) is proposed to provide an accurate and stable clock. The circuit will operate in three steps successively to charge sense capacitor, compare and change the difference between the voltage of sense capacitor and reference voltage into the alternation of VCO oscillation frequency, and discharge sense capacitor circularly. The above three steps will be repeated and the operating frequency of the VCO will be locked in the state that the charged voltage of sense capacitor is equal to the reference voltage VREF. Since the comparation between the voltage of sense capacitor and reference voltage is realized in one cycle of VCO’s output clock, the delay of comparator will not introduce random clock deviation and the circuit can achieve a more stable on chip clock. The proposed feedback loop frequency lock on-chip oscillator is designed using a 0.18 μm standard CMOS process, and the simulation results show that the frequency deviation is less than 0.6% in the temperature range of −40 – 125 °C when the oscillation of VCO is 525 KHz.