ACM Transactions on Reconfigurable Technology and Systems (TRETS)最新文献_第3页

Approaches for FPGA Design Assurance FPGA设计保证方法

ACM Transactions on Reconfigurable Technology and Systems (TRETS) Pub Date : 2021-12-28 DOI: 10.1145/3491233

Eli Cahill, B. Hutchings, Jeffrey B. Goeders

引用次数: 2

Scalable Phylogeny Reconstruction with Disaggregated Near-memory Processing 基于分解近记忆处理的可扩展系统发育重建

ACM Transactions on Reconfigurable Technology and Systems (TRETS) Pub Date : 2021-12-28 DOI: 10.1145/3484983

Nikolaos S. Alachiotis, P. Skrimponis, Manolis Pissadakis, D. Pnevmatikatos

{"title":"Scalable Phylogeny Reconstruction with Disaggregated Near-memory Processing","authors":"Nikolaos S. Alachiotis, P. Skrimponis, Manolis Pissadakis, D. Pnevmatikatos","doi":"10.1145/3484983","DOIUrl":"https://doi.org/10.1145/3484983","url":null,"abstract":"Disaggregated computer architectures eliminate resource fragmentation in next-generation datacenters by enabling virtual machines to employ resources such as CPUs, memory, and accelerators that are physically located on different servers. While this paves the way for highly compute- and/or memory-intensive applications to potentially deploy all CPUs and/or memory resources in a datacenter, it poses a major challenge to the efficient deployment of hardware accelerators: input/output data can reside on different servers than the ones hosting accelerator resources, thereby requiring time- and energy-consuming remote data transfers that diminish the gains of hardware acceleration. Targeting a disaggregated datacenter architecture similar to the IBM dReDBox disaggregated datacenter prototype, the present work explores the potential of deploying custom acceleration units adjacently to the disaggregated-memory controller on memory bricks (in dReDBox terminology), which is implemented on FPGA technology, to reduce data movement and improve performance and energy efficiency when reconstructing large phylogenies (evolutionary relationships among organisms). A fundamental computational kernel is the Phylogenetic Likelihood Function (PLF), which dominates the total execution time (up to 95%) of widely used maximum-likelihood methods. Numerous efforts to boost PLF performance over the years focused on accelerating computation; since the PLF is a data-intensive, memory-bound operation, performance remains limited by data movement, and memory disaggregation only exacerbates the problem. We describe two near-memory processing models, one that addresses the problem of workload distribution to memory bricks, which is particularly tailored toward larger genomes (e.g., plants and mammals), and one that reduces overall memory requirements through memory-side data interpolation transparently to the application, thereby allowing the phylogeny size to scale to a larger number of organisms without requiring additional memory.","PeriodicalId":162787,"journal":{"name":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127311834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs 基于二进制-一元混合计算的fpga近似常系数乘法

ACM Transactions on Reconfigurable Technology and Systems (TRETS) Pub Date : 2021-12-28 DOI: 10.1145/3494570

S. R. Faraji, Pierre Abillama, K. Bazargan

{"title":"Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs","authors":"S. R. Faraji, Pierre Abillama, K. Bazargan","doi":"10.1145/3494570","DOIUrl":"https://doi.org/10.1145/3494570","url":null,"abstract":"Multipliers are used in virtually all Digital Signal Processing (DSP) applications such as image and video processing. Multiplier efficiency has a direct impact on the overall performance of such applications, especially when real-time processing is needed, as in 4K video processing, or where hardware resources are limited, as in mobile and IoT devices. We propose a novel, low-cost, low energy, and high-speed approximate constant coefficient multiplier (CCM) using a hybrid binary-unary encoding method. The proposed method implements a CCM using simple routing networks with no logic gates in the unary domain, which results in more efficient multipliers compared to Xilinx LogiCORE IP CCMs and table-based KCM CCMs (Flopoco) on average. We evaluate the proposed multipliers on 2-D discrete cosine transform algorithm as a common DSP module. Post-routing FPGA results show that the proposed multipliers can improve the {area, area × delay, power consumption, and energy-delay product} of a 2-D discrete cosine transform on average by {30%, 33%, 30%, 31%}. Moreover, the throughput of the proposed 2-D discrete cosine transform is on average 5% more than that of the binary architecture implemented using table-based KCM CCMs. We will show that our method has fewer routability issues compared to binary implementations when implementing a DCT core.","PeriodicalId":162787,"journal":{"name":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114908847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

The Impact of Terrestrial Radiation on FPGAs in Data Centers 地面辐射对数据中心fpga的影响

ACM Transactions on Reconfigurable Technology and Systems (TRETS) Pub Date : 2021-12-06 DOI: 10.1145/3457198

Andrew M. Keller, M. Wirthlin

引用次数: 2

Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning Elastic-DF:通过自动分区的FPGA云中DNN推理的缩放性能

ACM Transactions on Reconfigurable Technology and Systems (TRETS) Pub Date : 2021-12-06 DOI: 10.1145/3470567

T. Alonso, L. Petrica, Mario Ruiz, Jakoba Petri-Koenig, Yaman Umuroglu, Ioannis Stamelos, Elias Koromilas, Michaela Blott, K. Vissers

{"title":"Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning","authors":"T. Alonso, L. Petrica, Mario Ruiz, Jakoba Petri-Koenig, Yaman Umuroglu, Ioannis Stamelos, Elias Koromilas, Michaela Blott, K. Vissers","doi":"10.1145/3470567","DOIUrl":"https://doi.org/10.1145/3470567","url":null,"abstract":"Customized compute acceleration in the datacenter is key to the wider roll-out of applications based on deep neural network (DNN) inference. In this article, we investigate how to maximize the performance and scalability of field-programmable gate array (FPGA)-based pipeline dataflow DNN inference accelerators (DFAs) automatically on computing infrastructures consisting of multi-die, network-connected FPGAs. We present Elastic-DF, a novel resource partitioning tool and associated FPGA runtime infrastructure that integrates with the DNN compiler FINN. Elastic-DF allocates FPGA resources to DNN layers and layers to individual FPGA dies to maximize the total performance of the multi-FPGA system. In the resulting Elastic-DF mapping, the accelerator may be instantiated multiple times, and each instance may be segmented across multiple FPGAs transparently, whereby the segments communicate peer-to-peer through 100 Gbps Ethernet FPGA infrastructure, without host involvement. When applied to ResNet-50, Elastic-DF provides a 44% latency decrease on Alveo U280. For MobileNetV1 on Alveo U200 and U280, Elastic-DF enables a 78% throughput increase, eliminating the performance difference between these cards and the larger Alveo U250. Elastic-DF also increases operating frequency in all our experiments, on average by over 20%. Elastic-DF therefore increases performance portability between different sizes of FPGA and increases the critical throughput per cost metric of datacenter inference.","PeriodicalId":162787,"journal":{"name":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129456046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs 请求、合并、服务和遗忘:fpga上带宽受限缓存不友好应用的缺失优化内存系统

ACM Transactions on Reconfigurable Technology and Systems (TRETS) Pub Date : 2021-12-01 DOI: 10.1145/3466823

Mikhail Asiatici, P. Ienne

{"title":"Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs","authors":"Mikhail Asiatici, P. Ienne","doi":"10.1145/3466823","DOIUrl":"https://doi.org/10.1145/3466823","url":null,"abstract":"Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by requesting each cache line only once, even when there are multiple misses corresponding to it. However, such reuse mechanism is traditionally implemented using an associative lookup. This limits the number of misses that are considered for reuse to a few tens, at most. In this article, we present an efficient pipeline that can process and store thousands of outstanding misses in cuckoo hash tables in on-chip SRAM with minimal stalls. This brings the same bandwidth advantage as a larger cache for a fraction of the area budget, because outstanding misses do not need a data array, which can significantly speed up irregular memory-bound latency-insensitive applications. In addition, we extend nonblocking caches to generate variable-length bursts to memory, which increases the bandwidth delivered by DRAMs and their controllers. The resulting miss-optimized memory system provides up to 25% speedup with 24× area reduction on 15 large sparse matrix-vector multiplication benchmarks evaluated on an embedded and a datacenter FPGA system.","PeriodicalId":162787,"journal":{"name":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124499278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure 在基于linux的云基础设施中部署多租户fpga

ACM Transactions on Reconfigurable Technology and Systems (TRETS) Pub Date : 2021-12-01 DOI: 10.1145/3474058

Joel Mandebi Mbongue, Danielle Tchuinkou Kwadjo, Alex Shuping, C. Bobda

{"title":"Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure","authors":"Joel Mandebi Mbongue, Danielle Tchuinkou Kwadjo, Alex Shuping, C. Bobda","doi":"10.1145/3474058","DOIUrl":"https://doi.org/10.1145/3474058","url":null,"abstract":"Cloud deployments now increasingly exploit Field-Programmable Gate Array (FPGA) accelerators as part of virtual instances. While cloud FPGAs are still essentially single-tenant, the growing demand for efficient hardware acceleration paves the way to FPGA multi-tenancy. It then becomes necessary to explore architectures, design flows, and resource management features that aim at exposing multi-tenant FPGAs to the cloud users. In this article, we discuss a hardware/software architecture that supports provisioning space-shared FPGAs in Kernel-based Virtual Machine (KVM) clouds. The proposed hardware/software architecture introduces an FPGA organization that improves hardware consolidation and support hardware elasticity with minimal data movement overhead. It also relies on VirtIO to decrease communication latency between hardware and software domains. Prototyping the proposed architecture with a Virtex UltraScale+ FPGA demonstrated near specification maximum frequency for on-chip data movement and high throughput in virtual instance access to hardware accelerators. We demonstrate similar performance compared to single-tenant deployment while increasing FPGA utilization, which is one of the goals of virtualization. Overall, our FPGA design achieved about 2× higher maximum frequency than the state of the art and a bandwidth reaching up to 28 Gbps on 32-bit data width.","PeriodicalId":162787,"journal":{"name":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114748539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Cloud Building Block Chip for Creating FPGA and ASIC Clouds 用于创建FPGA和ASIC云的云构建块芯片

ACM Transactions on Reconfigurable Technology and Systems (TRETS) Pub Date : 2021-12-01 DOI: 10.1145/3466822

A. Doğan, K. Ebcioglu

{"title":"Cloud Building Block Chip for Creating FPGA and ASIC Clouds","authors":"A. Doğan, K. Ebcioglu","doi":"10.1145/3466822","DOIUrl":"https://doi.org/10.1145/3466822","url":null,"abstract":"Hardware-accelerated cloud computing systems based on FPGA chips (FPGA cloud) or ASIC chips (ASIC cloud) have emerged as a new technology trend for power-efficient acceleration of various software applications. However, the operating systems and hypervisors currently used in cloud computing will lead to power, performance, and scalability problems in an exascale cloud computing environment. Consequently, the present study proposes a parallel hardware hypervisor system that is implemented entirely in special-purpose hardware, and that virtualizes application-specific multi-chip supercomputers, to enable virtual supercomputers to share available FPGA and ASIC resources in a cloud system. In addition to the virtualization of multi-chip supercomputers, the system’s other unique features include simultaneous migration of multiple communicating hardware tasks, and on-demand increase or decrease of hardware resources allocated to a virtual supercomputer. Partitioning the flat hardware design of the proposed hypervisor system into multiple partitions and applying the chip unioning technique to its partitions, the present study introduces a cloud building block chip that can be used to create FPGA or ASIC clouds as well. Single-chip and multi-chip verification studies have been done to verify the functional correctness of the hypervisor system, which consumes only a fraction of (10%) hardware resources.","PeriodicalId":162787,"journal":{"name":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","volume":"8 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123659673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Introduction to the Special Section on FPL 2019 FPL 2019特别部分介绍

ACM Transactions on Reconfigurable Technology and Systems (TRETS) Pub Date : 2021-07-29 DOI: 10.1145/3459587

X. Martorell, C. Álvarez, C. Bouganis, I. Sourdis

{"title":"Introduction to the Special Section on FPL 2019","authors":"X. Martorell, C. Álvarez, C. Bouganis, I. Sourdis","doi":"10.1145/3459587","DOIUrl":"https://doi.org/10.1145/3459587","url":null,"abstract":"Reconfigurable computing technologies, especially in the form of field-programmable gate arrays, have grown to become a mainstream technology for implementing large systems and accelerating applications. Modern programmable devices contain embedded memories, processors, arithmetic blocks, complex clocking structures, and advanced I/O interfaces, opening the door for new research opportunities and intricate engineering challenges. The International Conference on Field Programmable Logic and Applications (FPL) was the first and remains the largest conference covering the rapidly growing area of field-programmable logic and reconfigurable computing. FPL 2019 was held September 9–11, 2019, in Barcelona, Spain. In total, 152 papers were submitted from which the Program Committee selected 28 full papers and 28 poster papers for inclusion in the conference. The FPL Program co-Chairs and the General Chair invited the authors of the papers with the highest scores to submit an extended version of their FPL published work, by providing further details and/or experimentation for inclusion in a special issue. These papers bring results of recent research efforts in reconfigurable computing, in the areas of deep learning acceleration, multitenant field-programmable gate array attack mitigation, true-random number generation, and model checker acceleration. We would like to acknowledge the support of all reviewers in helping with paper selection and also for giving valuable suggestions. Special thanks also go to the authors who submitted papers and to the ACM TRETS support team. We would also like to thank Professor Deming Chen, Editorin-Chief of the ACM TRETS, for hosting this special issue.","PeriodicalId":162787,"journal":{"name":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122370446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Mitigating Voltage Attacks in Multi-Tenant FPGAs 缓解多租户fpga中的电压攻击

ACM Transactions on Reconfigurable Technology and Systems (TRETS) Pub Date : 2021-07-29 DOI: 10.1145/3451236

George Provelengios, Daniel E. Holcomb, R. Tessier

{"title":"Mitigating Voltage Attacks in Multi-Tenant FPGAs","authors":"George Provelengios, Daniel E. Holcomb, R. Tessier","doi":"10.1145/3451236","DOIUrl":"https://doi.org/10.1145/3451236","url":null,"abstract":"Recent research has exposed a number of security issues related to the use of FPGAs in embedded system and cloud computing environments. Circuits that deliberately waste power can be carefully crafted by a malicious cloud FPGA user and deployed to cause denial-of-service and fault injection attacks. The main defense strategy used by FPGA cloud services involves checking user-submitted designs for circuit structures that are known to aggressively consume power. Unfortunately, this approach is limited by an attacker’s ability to conceive new designs that defeat existing checkers. In this work, our contributions are twofold. We evaluate a variety of circuit power wasting techniques that typically are not flagged by design rule checks imposed by FPGA cloud computing vendors. The efficiencies of five power wasting circuits, including our new design, are evaluated in terms of power consumed per logic resource. We then show that the source of voltage attacks based on power wasters can be identified. Our monitoring approach localizes the attack and suppresses the clock signal for the target region within 21 μs, which is fast enough to stop an attack before it causes a board reset. All experiments are performed using a state-of-the-art Intel Stratix 10 FPGA.","PeriodicalId":162787,"journal":{"name":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115621843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9