Introduction to the Special Section on FPL 2019

Abstract

Reconfigurable computing technologies, especially in the form of field-programmable gate arrays, have grown to become a mainstream technology for implementing large systems and accelerating applications. Modern programmable devices contain embedded memories, processors, arithmetic blocks, complex clocking structures, and advanced I/O interfaces, opening the door for new research opportunities and intricate engineering challenges. The International Conference on Field Programmable Logic and Applications (FPL) was the first and remains the largest conference covering the rapidly growing area of field-programmable logic and reconfigurable computing. FPL 2019 was held September 9–11, 2019, in Barcelona, Spain. In total, 152 papers were submitted from which the Program Committee selected 28 full papers and 28 poster papers for inclusion in the conference. The FPL Program co-Chairs and the General Chair invited the authors of the papers with the highest scores to submit an extended version of their FPL published work, by providing further details and/or experimentation for inclusion in a special issue. These papers bring results of recent research efforts in reconfigurable computing, in the areas of deep learning acceleration, multitenant field-programmable gate array attack mitigation, true-random number generation, and model checker acceleration. We would like to acknowledge the support of all reviewers in helping with paper selection and also for giving valuable suggestions. Special thanks also go to the authors who submitted papers and to the ACM TRETS support team. We would also like to thank Professor Deming Chen, Editorin-Chief of the ACM TRETS, for hosting this special issue.