Proceedings of 1994 International Conference on Parallel and Distributed Systems最新文献

{"title":"A new approach of constructing information mutual exclusion in distributed systems","authors":"Hsiou-Mien Lien, S.-M. Yuan","doi":"10.1109/ICPADS.1994.590396","DOIUrl":"https://doi.org/10.1109/ICPADS.1994.590396","url":null,"abstract":"We present a decentralized, symmetric mutual exclusion algorithm in a computer network. The proposed algorithm has the same message complexity as that of the Maekawa's O(/spl radic/(N)) mutual exclusion algorithm ( Maekawa, 1985) and can be applied to arbitrary sizes of distributed systems. It is more suitable than Maekawa's when the symmetry of a system is a criticism. In addition, our algorithm has smaller request set size than that of Gupta, Bruell and Ghosh's (1987) mutual exclusion algorithm on a system of size 2/sup n/ for some integer n.","PeriodicalId":154429,"journal":{"name":"Proceedings of 1994 International Conference on Parallel and Distributed Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127418150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FDDI-M: a scheme to double FDDI's ability of supporting synchronous traffic","authors":"K. Shin, Q. Zheng","doi":"10.1109/ICPADS.1994.590109","DOIUrl":"https://doi.org/10.1109/ICPADS.1994.590109","url":null,"abstract":"Synchronous messages are usually generated periodically and each of them is required to be transmitted before the generation of the next message. Due to the inherent deficiency in its Medium Access Control (MAC) protocol, an FDDI token ring can use at most one half of its ring bandwidth to transmit such synchronous traffic. This deficiency greatly reduces the FDDI's capability of supporting multimedia applications like real-time voice/video transmissions. In this paper, we show how a few simple modifications to the FDDI's MAC protocol can remove this deficiency and double a ring's ability of supporting synchronous traffic. The modified protocol, called FDDI-M, preserves all other good features of an FDDI network and can also achieve a higher throughput for asynchronous traffic than the standard FDDI and the FDDI-II, thus making it useful even for those networks without heavy synchronous traffic.","PeriodicalId":154429,"journal":{"name":"Proceedings of 1994 International Conference on Parallel and Distributed Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126363472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Load balancing and query optimization in dataflow parallel evaluation of Datalog programs","authors":"J. F. A. Montes, E. Alba, J. M. Troya","doi":"10.1109/ICPADS.1994.590436","DOIUrl":"https://doi.org/10.1109/ICPADS.1994.590436","url":null,"abstract":"A dataflow model to obtain parallelism in the evaluation of Datalog is presented. This model performs query evaluation as a dataflow through a network of communicating concurrent processes capable of solving the query. This process network is based on the intensional database definition, plus the concrete query to be evaluated. A cost model to cope with the load balancing problem is described. A load balancing algorithm is presented and discussed. An algorithm to optimize the evaluation is described which is based on process network rewriting. This utilizes information in the query bindings to be evaluated in order to optimize the dataflow graph.","PeriodicalId":154429,"journal":{"name":"Proceedings of 1994 International Conference on Parallel and Distributed Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114631324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On parallel transaction processing in a coupled system","authors":"Ming-Syan Chen, Tao-Heng Yang, Philip S. Yu, Tze-Shiu Liu","doi":"10.1109/ICPADS.1994.590422","DOIUrl":"https://doi.org/10.1109/ICPADS.1994.590422","url":null,"abstract":"A performance study is conducted on parallel transaction processing in a coupled system, which is a multi-node system with a shared global buffer. We develop a multiple system simulator and obtain several performance results from it. This simulator has been run against three workloads, and the coupled system behavior with these three different inputs is studied. Several statistics, including those on local and global buffer hits, page writes to the global buffer, cross-invalidations and castouts, are comparatively analysed, and their relationship to the degree of data skew is explored.","PeriodicalId":154429,"journal":{"name":"Proceedings of 1994 International Conference on Parallel and Distributed Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128824721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experiences in session layer conformance testing","authors":"Ching-Sung Lu, San-Wei Sun, Raison Horne, Vivian Y. Chou, Kuan-Hsiung Liang, An-Tai Chang","doi":"10.1109/ICPADS.1994.590353","DOIUrl":"https://doi.org/10.1109/ICPADS.1994.590353","url":null,"abstract":"A protocol standard can be implemented by different manufacturers. Therefore, conformance testing of protocol implementations to standards is important to achieve the main purpose of the open systems interconnection. In this paper, after briefly introducing the session layer protocol and the conformance testing methodology we depict important errors found in the session layer implementations and the shortcomings of the test system.","PeriodicalId":154429,"journal":{"name":"Proceedings of 1994 International Conference on Parallel and Distributed Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128245957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A graph model for investigating memory consistency","authors":"Weiwu Hu","doi":"10.1109/ICPADS.1994.590364","DOIUrl":"https://doi.org/10.1109/ICPADS.1994.590364","url":null,"abstract":"The complexity of a multiprocessor memory system grows with the endeavors people make to improve the performance. The pseudo and real execution graphs introduced here can formally describe the complex event ordering behavior of the multiprocessor memory system and to verify the correctness of a parallel program under a consistency model. A pseudo execution graph represents the programmer's abstraction of an execution in which memory accesses are simple, atomic operations. A loop in the pseudo execution graph indicates an incorrect execution. A real execution graph represents the hardware designer's abstraction of an execution in which each memory access is a causal sequence of events. A loop in the real execution graph indicates that this execution is impossible to occur. A program is correct if all loops in the pseudo execution graphs cause loops in the corresponding real execution graphs.","PeriodicalId":154429,"journal":{"name":"Proceedings of 1994 International Conference on Parallel and Distributed Systems","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131750944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Keynote Address: The Prospects For Architecture-independent Parallel Programming","authors":"K. Kennedy","doi":"10.1109/ICPADS.1994.589874","DOIUrl":"https://doi.org/10.1109/ICPADS.1994.589874","url":null,"abstract":"Parallel computing has not lived up t o its promise. After nearly a decade of research, parallel systems are found primarily in research labs and only a few corporations have adopted it for their mainline computing problems. Significantly, very few independent software vendors have ported their codes t o parallel machines. Now high-performance workstations are rapidly gaining on high-end supercomputing systems and we are undergoing a shakeout among the vendors of parallel computer systems. Is parallel computing dead? In this address, I will argue that i t is premature t o declare its demise, but that key software problems need to be addressed if it is t o succeed. Foremost among these is the problem of support for architecture-independent parallel programming. Software developers need t o be able t o rely on the retargetability of their codes for new parallel machines as they emerge. The absence of such assurance has been the prime reason for the limited acceptance of scalable parallelism to date. As an example, I will discuss High Performance Fortran, which is designed to support the construction of architecture-independent data-parallel programs. High Performance Fortran extends Fortran 90 by providing a set of statements that specify the distribution of data structures across the processor array. From this specification, the compiler automatically derives parallelism according to the “owner computes” rule, which specifies that a computation should be performed on a processor that owns most of the data involved in the computation. Although over twenty companies are working on products related t o High Performance Fortran, its success is not yet guaranteed. To be widely accepted, High Performance Fortran will need a very sophisticated compiler technology. In addition, it needs additional features to increase the breadth of coverage t o include irregular problems, task parallelism, and high-performance input/output. I will survey the current strategies for meeting these needs and describe the tools needed to make programming in Fortran D accessible t o the average scientist or engineer. The talk will conclude with a discussion of the long-term prospects for scalable parallel computation and the software needed t o make it practical.","PeriodicalId":154429,"journal":{"name":"Proceedings of 1994 International Conference on Parallel and Distributed Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130648456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integrated support to improve inter-thread communication and synchronization in a multithreaded processor","authors":"C.-S. Chen, C.-C. Tseng","doi":"10.1109/ICPADS.1994.590359","DOIUrl":"https://doi.org/10.1109/ICPADS.1994.590359","url":null,"abstract":"This paper presents an integrated compiler, runtime control, and hardware solution to improve inter-thread communication and synchronization in a multithreaded processor architecture. Multithreading improves processor utilization by exploiting more parallelism. The improvement in utilization, however, is hindered by interthread communication and synchronization problems, which incur extra communication overhead and thus degrade the performance of the system. In this paper, we propose efficient inter-thread communication and synchronization schemes based on a superscalar DLX processor with multithreading functionality. Compiler, runtime control, and hardware support used in the schemes are discussed. Simulations are presented to show the effectiveness of the proposed schemes.","PeriodicalId":154429,"journal":{"name":"Proceedings of 1994 International Conference on Parallel and Distributed Systems","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117268073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Techniques to tackle state explosion in global predicate detection","authors":"S. Alagar, S. Venkatesan","doi":"10.1109/ICPADS.1994.590349","DOIUrl":"https://doi.org/10.1109/ICPADS.1994.590349","url":null,"abstract":"Detecting properties about a distributed program is an important problem in testing and debugging distributed programs. This problem is very hard due to the combinatorial explosion of the global state space. For a given execution, we consider the problem of detecting whether a predicate /spl Phi/ is true at some global state of the system. First, we present a space efficient algorithm for detecting /spl Phi/. Next, we present a parallel algorithm to reduce the time taken to detect /spl Phi/. We then improve the performance of our algorithms, both in space and time, by increasing the granularity of the execution step from an event to a sequence of events in a process.","PeriodicalId":154429,"journal":{"name":"Proceedings of 1994 International Conference on Parallel and Distributed Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116250540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Communication-efficient implementation of block recursive algorithms on distributed-memory machines","authors":"S. Gupta, Chua-Huang Huang, Rodney W. Johnson, P. Sadayappan","doi":"10.1109/ICPADS.1994.590060","DOIUrl":"https://doi.org/10.1109/ICPADS.1994.590060","url":null,"abstract":"This paper presents a design methodology for developing efficient distributed-memory parallel programs for block-recursive algorithms such as the fast Fourier transform and bitonic sort. This design methodology is specifically suited for most modern supercomputers having a distributed-memory architecture with circuit-switched or wormhole routed mesh or hypercube interconnection network. A mathematical framework based on the tenser product and other matrix operations is used for representing algorithms. Communication-efficient implementations with effectively overlapped computation and communication are achieved by manipulating the mathematical representation using the tenser algebra. Performance results for FFT programs on the Intel iPSC/860 and Intel Paragon are presented.","PeriodicalId":154429,"journal":{"name":"Proceedings of 1994 International Conference on Parallel and Distributed Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116271410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}