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Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)最新文献

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Semi-formal test generation with Genevieve 用Genevieve生成半正式测试
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.379035
J. Dushina, M. Benjamin, D. Geist
{"title":"Semi-formal test generation with Genevieve","authors":"J. Dushina, M. Benjamin, D. Geist","doi":"10.1145/378239.379035","DOIUrl":"https://doi.org/10.1145/378239.379035","url":null,"abstract":"This paper describes the first application of the Genevieve test generation methodology. The Genevieve approach uses semi-formal techniques derived from \"model-checking\" to generate test suites for specific behaviours of the design under test. An \"interesting\" behaviour is claimed to be unreachable. If a path from an initial state to the state of interest does exist, a counter-example is generated. The sequence of states specifies a test for the desired behaviour. To highlight real problems that could appear during test generation, we chose the Store Data Unit (SDU) of the ST100, a new high performance digital signal processor (DSP) developed by STMicroelectronics. This unit is specifically selected because of the following key issues: 1. big data structures that can not be directly modelled without state explosion, 2. complex control logic that would require an excessive number of tests to exercise exhaustively, 3. a design where it is difficult to determine how to drive the complete system to ensure a given behaviour in the unit under test. The Genevieve methodology allowed us to define a coverage model specifically devoted to covering corner cases of the design. Hence the generated test suite achieved very efficient coverage of corner cases, and checked not only functional correctness but also whether the implementation matched design intent. As a result the Genevieve tests discovered some subtle performance bugs which would otherwise be very difficult to find.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123550003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Chaff: engineering an efficient SAT solver 谷壳:工程一个有效的SAT求解器
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.379017
M. Moskewicz, Conor F. Madigan, Ying Zhao, Lintao Zhang, S. Malik
{"title":"Chaff: engineering an efficient SAT solver","authors":"M. Moskewicz, Conor F. Madigan, Ying Zhao, Lintao Zhang, S. Malik","doi":"10.1145/378239.379017","DOIUrl":"https://doi.org/10.1145/378239.379017","url":null,"abstract":"Boolean satisfiability is probably the most studied of the combinatorial optimization/search problems. Significant effort has been devoted to trying to provide practical solutions to this problem for problem instances encountered in a range of applications in electronic design automation (EDA), as well as in artificial intelligence (AI). This study has culminated in the development of several SAT packages, both proprietary and in the public domain (e.g. GRASP, SATO) which find significant use in both research and industry. Most existing complete solvers are variants of the Davis-Putnam (DP) search algorithm. In this paper we describe the development of a new complete solver, Chaff which achieves significant performance gains through careful engineering of all aspects of the search-especially a particularly efficient implementation of Boolean constraint propagation (BCP) and a novel low overhead decision strategy. Chaff has been able to obtain one to two orders of magnitude performance improvement on difficult SAT benchmarks in comparison with other solvers (DP or otherwise), including GRASP and SATO.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128263964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3715
Dynamic power management in a mobile multimedia system with guaranteed quality-of-service 移动多媒体系统中保证服务质量的动态电源管理
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1109/DAC.2001.156252
Qinru Qiu, Qing Wu, Massoud Pedram
{"title":"Dynamic power management in a mobile multimedia system with guaranteed quality-of-service","authors":"Qinru Qiu, Qing Wu, Massoud Pedram","doi":"10.1109/DAC.2001.156252","DOIUrl":"https://doi.org/10.1109/DAC.2001.156252","url":null,"abstract":"In this paper we address the problem of dynamic power management in a distributed multimedia system with a required quality of service (QoS). Using a generalized stochastic Petri net model where the non-exponential inter-arrival time distribution of the incoming requests is captured by the \"stage method\", we provide a detailed model of the power-managed multimedia system under general QoS constraints. Based on this mathematical model, the power-optimal policy is obtained by solving a linear programming problem. We compare the new problem formulation and solution technique to previous dynamic power management techniques that can only optimize power under delay constraints. We then demonstrate that these other techniques yield policies with higher power dissipation by over-constraining the delay target in an attempt to indirectly satisfy the QoS constraints. In contrast, our new method correctly formulates the power management problem under QoS constraints and obtains the optimal solution.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125667402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
Teaching future verification engineers: the forgotten side of logic design 教导未来的验证工程师:逻辑设计被遗忘的一面
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378477
F. Özgüner, D. Marhefka, J. DeGroat, Bruce Wile, Jennifer Stofer, Lyle Hanrahan
{"title":"Teaching future verification engineers: the forgotten side of logic design","authors":"F. Özgüner, D. Marhefka, J. DeGroat, Bruce Wile, Jennifer Stofer, Lyle Hanrahan","doi":"10.1145/378239.378477","DOIUrl":"https://doi.org/10.1145/378239.378477","url":null,"abstract":"This paper describes a senior/graduate level course in hardware logic verification being offered by The Ohio State University in cooperation with IBM. The need for the course is established through the growing importance of logic verification to users of custom logic designs. We discuss the short-term and long-term goals for the course, and describe the course content and format. The course relies heavily on lab projects to illustrate the main concepts. Three projects and a final project review are described.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130263917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A framework for object oriented hardware specification, verification, and synthesis 一个面向对象硬件规范、验证和综合的框架
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378537
T. Kuhn, Tobias Oppold, M. Winterholer, W. Rosenstiel, Mark Edwards, Y. Kashai
{"title":"A framework for object oriented hardware specification, verification, and synthesis","authors":"T. Kuhn, Tobias Oppold, M. Winterholer, W. Rosenstiel, Mark Edwards, Y. Kashai","doi":"10.1145/378239.378537","DOIUrl":"https://doi.org/10.1145/378239.378537","url":null,"abstract":"We describe two things. First, we present a uniform framework for object oriented specification and verification of hardware. For this purpose the object oriented language 'e' is introduced along with a powerful run-time environment that enables the designer to perform the verification task. Second, we present an object oriented synthesis that enhances 'e' and its dedicated run-time environment into a framework for specification, verification, and synthesis. The usability of our approach is demonstrated by real-world examples.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126296102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Inductance 101: modeling and extraction 电感101:建模和提取
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378500
M. Beattie, L. Pileggi
{"title":"Inductance 101: modeling and extraction","authors":"M. Beattie, L. Pileggi","doi":"10.1145/378239.378500","DOIUrl":"https://doi.org/10.1145/378239.378500","url":null,"abstract":"Modeling magnetic interactions for on-chip interconnect has become an issue of great interest for integrated circuit design in recent years. This tutorial paper describes the basic concepts of magnetic interaction, loop and partial inductance, along with some of the high frequency effects such as the skin and proximity effect.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126059404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 86
Reticle enhancement technology: implications and challenges for physical design 光栅增强技术:物理设计的意义和挑战
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378332
W. Grobman, M. Thompson, R. Wang, C. Yuan, Ruiqi Tian, E. Demircan
{"title":"Reticle enhancement technology: implications and challenges for physical design","authors":"W. Grobman, M. Thompson, R. Wang, C. Yuan, Ruiqi Tian, E. Demircan","doi":"10.1145/378239.378332","DOIUrl":"https://doi.org/10.1145/378239.378332","url":null,"abstract":"In this paper, we review phase shift lithography, rule vs. model based methods for OPC and model-based tiling, and discuss their implications for layout and verification. We will discuss novel approaches, using polarizing films on reticles, which change the game for phase-shift coloring, and could lead to a new direction in c:PSM constraints on physical design. We emphasize the need to do tiling that is model-driven and uses optimization techniques to achieve planarity for better manufacturing tolerance in the subwavelength dimensions era. Electromagnetic solver results will be presented which estimate the effect of tiling on circuit timing.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126810712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Using symbolic algebra in algorithmic level DSP synthesis 符号代数在算法级DSP合成中的应用
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378485
A. Peymandoust, G. Micheli
{"title":"Using symbolic algebra in algorithmic level DSP synthesis","authors":"A. Peymandoust, G. Micheli","doi":"10.1145/378239.378485","DOIUrl":"https://doi.org/10.1145/378239.378485","url":null,"abstract":"Current multimedia applications require the design of data-path intensive circuits. Unfortunately, current design tools and methods support design abstraction at a level that is inferior to the expectation of designers. Namely, most arithmetic-level optimizations are not supported and they are left to the designers' ingenuity. In this paper, we show how symbolic algebra can be used to construct an arithmetic-level decomposition algorithm. We also introduce our tool, SymSyn, that performs arithmetic library mapping and optimization of data-flow descriptions into data paths using arithmetic components.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122894462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
Watermarking graph partitioning solutions 水印图划分解决方案
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378567
Gregory Wolfe, J. Wong, M. Potkonjak
{"title":"Watermarking graph partitioning solutions","authors":"Gregory Wolfe, J. Wong, M. Potkonjak","doi":"10.1145/378239.378567","DOIUrl":"https://doi.org/10.1145/378239.378567","url":null,"abstract":"Trends in the semiconductor industry towards extensive design and code reuse motivate a need for adequate intellectual property protection (IPP) schemes. We offer a new general IPP scheme called constraint-based watermarking and analyze it in the context of the graph partitioning problem. Graph partitioning is a critical optimization problem that has many applications, particularly in the semiconductor design process. Our IPP technique for graph partitioning watermarks solutions to graph partitioning problems so that they carry an author's signature. Our technique is transparent to the actual CAD tool which does the partitioning. Our technique produces solutions that have very low quality degradation levels, yet carry signatures that are convincingly unambiguous, extremely unlikely to be present by coincidence, and difficult to detect or remove without completely resolving the partitioning problem.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127021573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit symmetric block ciphers 基于故障的128位对称分组密码侧信道并发错误检测
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.379027
R. Karri, Kaijie Wu, P. Mishra, Yongkook Kim
{"title":"Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit symmetric block ciphers","authors":"R. Karri, Kaijie Wu, P. Mishra, Yongkook Kim","doi":"10.1145/378239.379027","DOIUrl":"https://doi.org/10.1145/378239.379027","url":null,"abstract":"Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for symmetric encryption algorithms based on the inverse relationship that exists between encryption and decryption at algorithm level, round level and operation level and develop CED architectures that explore the trade-off between area overhead, performance penalty and error detection latency. The proposed techniques have been validated on FPGA implementations of AES finalist 128-bit symmetric encryption algorithms.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132553150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 64
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